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[46.33.159.2]) by mx.google.com with ESMTPSA id dj7sm597075wib.6.2013.05.09.19.19.26 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 09 May 2013 19:19:27 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Cc: Stefano.Stabellini@eu.citrix.com, ian.campbell@citrix.com, patches@linaro.org, Julien Grall Subject: [PATCH V3 18/41] xen/arm: Introduce gic_route_dt_irq Date: Fri, 10 May 2013 03:18:04 +0100 Message-Id: <1368152307-598-19-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1368152307-598-1-git-send-email-julien.grall@linaro.org> References: <1368152307-598-1-git-send-email-julien.grall@linaro.org> X-Gm-Message-State: ALoCoQkv9x7yFJWDmnVee6j1W0p3VvZqWoMVWwVuQ9a9iuNjE+ds/L5QRz1F2fAm46oqgFBnCyS+ X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c02::231 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This function routes an IRQ to a specific cpu. The IRQ is retrieved via the device tree. Signed-off-by: Julien Grall Acked-by: Ian Campbell Changes in v3: - Rename dt_irq_is_level_trigger to dt_irq_is_level_triggered Changes in v2: - Use dt_irq_is_level_trigger instead of the old name irq_is_level_trigger --- xen/arch/arm/gic.c | 11 +++++++++++ xen/include/asm-arm/gic.h | 5 +++++ 2 files changed, 16 insertions(+) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index eeb526e..06ba78c 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -238,6 +238,17 @@ static int gic_route_irq(unsigned int irq, bool_t level, return 0; } +/* Program the GIC to route an interrupt with a dt_irq */ +void gic_route_dt_irq(const struct dt_irq *irq, unsigned int cpu_mask, + unsigned int priority) +{ + bool_t level; + + level = dt_irq_is_level_triggered(irq); + + gic_route_irq(irq->irq, level, cpu_mask, priority); +} + static void __init gic_dist_init(void) { uint32_t type; diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 3efb2b5..78dd21a 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -133,6 +133,8 @@ #define VGIC_IRQ_EVTCHN_CALLBACK 31 #ifndef __ASSEMBLY__ +#include + extern int domain_vgic_init(struct domain *d); extern void domain_vgic_free(struct domain *d); @@ -142,6 +144,9 @@ extern void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq,int virtual); extern void vgic_clear_pending_irqs(struct vcpu *v); extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq); +/* Program the GIC to route an interrupt with a dt_irq */ +extern void gic_route_dt_irq(const struct dt_irq *irq, unsigned int cpu_mask, + unsigned int priority); extern void gic_route_ppis(void); extern void gic_route_spis(void);