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[46.33.159.2]) by mx.google.com with ESMTPSA id m3sm508537wij.5.2013.06.24.16.04.47 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 24 Jun 2013 16:04:48 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Cc: ian.campbell@citrix.com, Stefano.Stabellini@eu.citrix.com, patches@linaro.org, Stefano Stabellini , Julien Grall Subject: [PATCH 2/5] xen/arm: Keep count of inflight interrupts Date: Tue, 25 Jun 2013 00:04:23 +0100 Message-Id: <1372115067-17071-3-git-send-email-julien.grall@citrix.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1372115067-17071-1-git-send-email-julien.grall@citrix.com> References: <1372115067-17071-1-git-send-email-julien.grall@citrix.com> X-Gm-Message-State: ALoCoQnEUcKyrtEq5O31SEZskituiR/gmY3wViCUvzg5VRi2NYSoDgxwQ5sevMJWzyRWrJynIZwW X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c01::236 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Stefano Stabellini For guest's timers (both virtual and physical), Xen will inject virtual interrupt. Linux handles timer interrupt as: 1) Receive the interrupt and ack it 2) Handle the current event timer 3) Set the next event timer 4) EOI the interrupt It's unlikely possible to reinject another interrupt before the previous one is EOIed because the next deadline is shorter than the time to execute code until EOI it. Signed-off-by: Stefano Stabellini Signed-off-by: Julien Grall --- xen/arch/arm/gic.c | 35 +++++++++++++++++++++++------------ xen/arch/arm/vgic.c | 1 + xen/include/asm-arm/domain.h | 2 ++ 3 files changed, 26 insertions(+), 12 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 0fee3f2..21575df 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -817,7 +817,7 @@ static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *r while ((i = find_next_bit((const long unsigned int *) &eisr, 64, i)) < 64) { - struct pending_irq *p; + struct pending_irq *p, *n; int cpu, eoi; cpu = -1; @@ -826,13 +826,32 @@ static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *r spin_lock_irq(&gic.lock); lr = GICH[GICH_LR + i]; virq = lr & GICH_LR_VIRTUAL_MASK; + + p = irq_to_pending(v, virq); + if ( p->desc != NULL ) { + p->desc->status &= ~IRQ_INPROGRESS; + /* Assume only one pcpu needs to EOI the irq */ + cpu = p->desc->arch.eoi_cpu; + eoi = 1; + pirq = p->desc->irq; + } + if ( !atomic_dec_and_test(&p->inflight_cnt) ) + { + /* Physical IRQ can't be reinject */ + WARN_ON(p->desc != NULL); + gic_set_lr(i, p->irq, GICH_LR_PENDING, p->priority); + spin_unlock_irq(&gic.lock); + i++; + continue; + } + GICH[GICH_LR + i] = 0; clear_bit(i, &this_cpu(lr_mask)); if ( !list_empty(&v->arch.vgic.lr_pending) ) { - p = list_entry(v->arch.vgic.lr_pending.next, typeof(*p), lr_queue); - gic_set_lr(i, p->irq, GICH_LR_PENDING, p->priority); - list_del_init(&p->lr_queue); + n = list_entry(v->arch.vgic.lr_pending.next, typeof(*n), lr_queue); + gic_set_lr(i, n->irq, GICH_LR_PENDING, n->priority); + list_del_init(&n->lr_queue); set_bit(i, &this_cpu(lr_mask)); } else { gic_inject_irq_stop(); @@ -840,14 +859,6 @@ static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *r spin_unlock_irq(&gic.lock); spin_lock_irq(&v->arch.vgic.lock); - p = irq_to_pending(v, virq); - if ( p->desc != NULL ) { - p->desc->status &= ~IRQ_INPROGRESS; - /* Assume only one pcpu needs to EOI the irq */ - cpu = p->desc->arch.eoi_cpu; - eoi = 1; - pirq = p->desc->irq; - } list_del_init(&p->inflight); spin_unlock_irq(&v->arch.vgic.lock); diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 7eaccb7..2d91dce 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -672,6 +672,7 @@ void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq, int virtual) spin_lock_irqsave(&v->arch.vgic.lock, flags); + atomic_inc(&n->inflight_cnt); /* vcpu offline or irq already pending */ if (test_bit(_VPF_down, &v->pause_flags) || !list_empty(&n->inflight)) { diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 339b6e6..fa0b776 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -8,6 +8,7 @@ #include #include #include +#include /* Represents state corresponding to a block of 32 interrupts */ struct vgic_irq_rank { @@ -21,6 +22,7 @@ struct vgic_irq_rank { struct pending_irq { int irq; + atomic_t inflight_cnt; struct irq_desc *desc; /* only set it the irq corresponds to a physical irq */ uint8_t priority; /* inflight is used to append instances of pending_irq to