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[46.33.159.2]) by mx.google.com with ESMTPSA id d8sm16671187wiz.0.2013.07.18.06.35.58 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 18 Jul 2013 06:36:00 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Cc: ian.campbell@citrix.com, Stefano.Stabellini@eu.citrix.com, patches@linaro.org, Julien Grall Subject: [PATCH v3] xen/arm: Implement MPIDR per VCPU Date: Thu, 18 Jul 2013 14:33:43 +0100 Message-Id: <1374154423-8710-1-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 X-Gm-Message-State: ALoCoQkK+jL2mVLVJDtgjfk/iqKcItQzBFXuMtZqzwPss2znSXG9OexWrk423m1EoKTNHRe/Qu83 X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.46 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Use different affinity for each VCPU and always expose an SMP systems to the guest. Signed-off-by: Julien Grall --- Changes in v3: - vmpidr should be a register_t Changes in v2: - Create a virtual MPIDR during the VCPU initialization --- xen/arch/arm/domain.c | 10 ++++++++-- xen/include/asm-arm/domain.h | 2 +- xen/include/asm-arm/processor.h | 9 +++++++++ 3 files changed, 18 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 6937abf..bcf1755 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -140,7 +140,7 @@ static void ctxt_switch_to(struct vcpu *n) isb(); WRITE_SYSREG32(n->domain->arch.vpidr, VPIDR_EL2); - WRITE_SYSREG(n->domain->arch.vmpidr, VMPIDR_EL2); + WRITE_SYSREG(n->arch.vmpidr, VMPIDR_EL2); /* VGIC */ gic_restore_state(n); @@ -451,7 +451,14 @@ int vcpu_initialise(struct vcpu *v) return rc; v->arch.sctlr = SCTLR_BASE; + /* + * By default exposes an SMP system with AFFO set to the VCPU ID + * TODO: Handle multi-threading processor and cluster + */ + v->arch.vmpidr = MPIDR_SMP | (v->vcpu_id << MPIDR_AFF0_SHIFT); + v->arch.actlr = READ_SYSREG32(ACTLR_EL1); + /* XXX: Handle other than CA15 cpus */ if ( v->domain->max_vcpus > 1 ) v->arch.actlr |= ACTLR_CA15_SMP; @@ -490,7 +497,6 @@ int arch_domain_create(struct domain *d, unsigned int domcr_flags) /* Default the virtual ID to match the physical */ d->arch.vpidr = boot_cpu_data.midr.bits; - d->arch.vmpidr = boot_cpu_data.mpidr.bits; clear_page(d->shared_info); share_xen_page_with_guest( diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 339b6e6..1049282 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -68,7 +68,6 @@ struct arch_domain /* Virtual CPUID */ uint32_t vpidr; - register_t vmpidr; struct { uint64_t offset; @@ -194,6 +193,7 @@ struct arch_vcpu /* CP 15 */ uint32_t csselr; + register_t vmpidr; uint32_t gic_hcr, gic_vmcr, gic_apr; uint32_t gic_lr[64]; diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 263bd03..5181e7b 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -3,6 +3,15 @@ #include +/* MIDR Main ID Register */ +#define MIDR_MASK 0xff0ffff0 + +/* MPIDR Multiprocessor Affinity Register */ +#define MPIDR_UP (1 << 30) +#define MPIDR_SMP (1 << 31) +#define MPIDR_AFF0_SHIFT (0) +#define MPIDR_AFF0_MASK (0xff << MPIDR_AFF0_SHIFT) + /* TTBCR Translation Table Base Control Register */ #define TTBCR_EAE 0x80000000 #define TTBCR_N_MASK 0x07