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(firewall.ctxuk.citrix.com. [46.33.159.2]) by mx.google.com with ESMTPSA id a4sm4503573wik.11.2013.08.06.11.31.26 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 06 Aug 2013 11:31:26 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Cc: stefano.stabellini@eu.citrix.com, ian.campbell@citrix.com, patches@linaro.org, tim@xen.org, Julien Grall Subject: [PATCH v4 2/2] xen/arm: errata 766422: decode thumb store during data abort Date: Tue, 6 Aug 2013 19:31:18 +0100 Message-Id: <1375813878-21435-3-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1375813878-21435-1-git-send-email-julien.grall@linaro.org> References: <1375813878-21435-1-git-send-email-julien.grall@linaro.org> MIME-Version: 1.0 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , >From the errata document: When a non-secure non-hypervisor memory operation instruction generates a stage2 page table translation fault, a trap to the hypervisor will be triggered. For an architecturally defined subset of instructions, the Hypervisor Syndrome Register (HSR) will have the Instruction Syndrome Valid (ISV) bit set to 1’b1, and the Rt field should reflect the source register (for stores) or destination register for loads. On Cortex-A15, for Thumb and ThumbEE stores, the Rt value may be incorrect and should not be used, even if the ISV bit is set. All loads, and all ARM instruction set loads and stores, will have the correct Rt value if the ISV bit is set. To avoid this issue, Xen needs to decode thumb store instruction and update the transfer register. Signed-off-by: Julien Grall Acked-by: Ian Campbell --- Changes in v3: - Use unlikely to check if the processor is affected by the errata - Move the decoder in another patch and use it Changes in v2: - Only decode the instruction on affected processor - Handle ARM 32-bit instruction in read_instruction --- xen/arch/arm/traps.c | 12 ++++++++++++ xen/include/asm-arm/arm32/processor.h | 4 ++++ xen/include/asm-arm/arm64/processor.h | 2 ++ 3 files changed, 18 insertions(+) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 6b5fa51..47e9ba4 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -36,6 +36,7 @@ #include #include +#include "decode.h" #include "io.h" #include "vtimer.h" #include @@ -1336,6 +1337,17 @@ static void do_trap_data_abort_guest(struct cpu_user_regs *regs, if ( !dabt.valid ) goto bad_data_abort; + /* + * Errata 766422: Thumb store translation fault to Hypervisor may + * not have correct HSR Rt value. + */ + if ( cpu_has_errata_766422() && (regs->cpsr & PSR_THUMB) && dabt.write ) + { + rc = decode_instruction(regs, &info.dabt); + if ( rc ) + goto bad_data_abort; + } + if (handle_mmio(&info)) { advance_pc(regs, hsr); diff --git a/xen/include/asm-arm/arm32/processor.h b/xen/include/asm-arm/arm32/processor.h index b266252..a21d104 100644 --- a/xen/include/asm-arm/arm32/processor.h +++ b/xen/include/asm-arm/arm32/processor.h @@ -111,6 +111,10 @@ struct cpu_user_regs #define READ_SYSREG(R...) READ_SYSREG32(R) #define WRITE_SYSREG(V, R...) WRITE_SYSREG32(V, R) +/* Errata 766422: only Cortex A15 r0p4 is affected */ +#define cpu_has_errata_766422() \ + (unlikely(current_cpu_data.midr.bits == 0x410fc0f4)) + #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARM_ARM32_PROCESSOR_H */ diff --git a/xen/include/asm-arm/arm64/processor.h b/xen/include/asm-arm/arm64/processor.h index c8d4609..5d9b952 100644 --- a/xen/include/asm-arm/arm64/processor.h +++ b/xen/include/asm-arm/arm64/processor.h @@ -104,6 +104,8 @@ struct cpu_user_regs #define READ_SYSREG(name) READ_SYSREG64(name) #define WRITE_SYSREG(v, name) WRITE_SYSREG64(v, name) +#define cpu_has_errata_766422() 0 + #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARM_ARM64_PROCESSOR_H */