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([185.25.64.249]) by mx.google.com with ESMTPSA id i5sm25524370wiw.7.1969.12.31.16.00.00 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 27 Aug 2013 05:13:39 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Cc: stefano.stabellini@eu.citrix.com, ian.campbell@citrix.com, patches@linaro.org, andre.przywara@linaro.org, Julien Grall Subject: [PATCH] drivers/char: pl011: Enable receive timeout interrupt Date: Tue, 27 Aug 2013 13:13:35 +0100 Message-Id: <1377605615-8424-1-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.48 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The commit 874f76a "PL011: fix reverse logic for interrupt mask register" introduced regression on the Versatile Express. The board didn't receive correctly input. The timeout interrupt may be asserted when the FIFO is not empty, and no futher data is received over a 32-bit period. Signed-off-by: Julien Grall --- xen/drivers/char/pl011.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c index 0e1eb64..e4bd702 100644 --- a/xen/drivers/char/pl011.c +++ b/xen/drivers/char/pl011.c @@ -140,7 +140,7 @@ static void __init pl011_init_postirq(struct serial_port *port) pl011_write(uart, ICR, OEI|BEI|PEI|FEI); /* Unmask interrupts */ - pl011_write(uart, IMSC, OEI|BEI|PEI|FEI|TXI|RXI); + pl011_write(uart, IMSC, RTI|OEI|BEI|PEI|FEI|TXI|RXI); } static void pl011_suspend(struct serial_port *port)