From patchwork Thu Sep 18 22:50:04 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roy Franz X-Patchwork-Id: 37622 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wg0-f70.google.com (mail-wg0-f70.google.com [74.125.82.70]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 05AD32054E for ; Thu, 18 Sep 2014 22:52:52 +0000 (UTC) Received: by mail-wg0-f70.google.com with SMTP id n12sf1027199wgh.1 for ; Thu, 18 Sep 2014 15:52:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:date:message-id:in-reply-to :references:cc:subject:precedence:list-id:list-unsubscribe:list-post :list-help:list-subscribe:mime-version:sender:errors-to :x-original-sender:x-original-authentication-results:mailing-list :list-archive:content-type:content-transfer-encoding; bh=W0kLlrKlh0nNLfbQ3HHBFgDDgmS0OrCakp2nOZHqfxA=; b=Ip2oMZwXds5Pj0TwfHZahUxWrJmo0SJRlA+ZqSXd0C+A1Tl6QqYvE1wqIj2WtiytnT xrFuTDdyElBPkYr4ncOSV35fXy6VxzdE+K84rL+QlYTuhsFsxT79khw2j7XO1/wyPrSZ CfELsLavZ2c2mn8S0QHOkgvAlD/36On1qxr1kNcejm8cLddKXQLuXopKQ51BOdM+7QEK i0mWHExCvGQB2JkFjWmhAeaewGEKMcmiVB28+5G7/qK+yBoqvpLTaM1tz8uPc6uNNh8o cBpAYHOvB0rqVq8Gz4Aa7+5G6v30vXz6C/ScfJOUUYwEIWyrgJBXcqgNPo7taDpLpV6y lSgA== X-Gm-Message-State: ALoCoQnc3FJFuaKyPDDiN7+S1VMp143ECOpsxADcX29fNHAGFnv8CDhqLuBCkkqQmjPywJ2Vcmiz X-Received: by 10.180.88.8 with SMTP id bc8mr1368247wib.0.1411080772240; Thu, 18 Sep 2014 15:52:52 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.5.38 with SMTP id p6ls278913lap.72.gmail; Thu, 18 Sep 2014 15:52:51 -0700 (PDT) X-Received: by 10.152.19.66 with SMTP id c2mr2875442lae.64.1411080771956; Thu, 18 Sep 2014 15:52:51 -0700 (PDT) Received: from mail-lb0-f172.google.com (mail-lb0-f172.google.com [209.85.217.172]) by mx.google.com with ESMTPS id w4si75440lag.128.2014.09.18.15.52.51 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 18 Sep 2014 15:52:51 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.172 as permitted sender) client-ip=209.85.217.172; Received: by mail-lb0-f172.google.com with SMTP id p9so1464609lbv.17 for ; Thu, 18 Sep 2014 15:52:51 -0700 (PDT) X-Received: by 10.152.42.136 with SMTP id o8mr2597830lal.71.1411080771896; Thu, 18 Sep 2014 15:52:51 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.130.169 with SMTP id of9csp843174lbb; Thu, 18 Sep 2014 15:52:51 -0700 (PDT) X-Received: by 10.52.146.17 with SMTP id sy17mr1423784vdb.29.1411080770649; Thu, 18 Sep 2014 15:52:50 -0700 (PDT) Received: from lists.xen.org (lists.xen.org. [50.57.142.19]) by mx.google.com with ESMTPS id fa8si79307vdc.20.2014.09.18.15.52.50 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 18 Sep 2014 15:52:50 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XUkX8-0006Uu-0d; Thu, 18 Sep 2014 22:50:38 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XUkX5-0006P1-76 for xen-devel@lists.xen.org; Thu, 18 Sep 2014 22:50:35 +0000 Received: from [85.158.137.68:37922] by server-5.bemta-3.messagelabs.com id CB/FA-30889-AB16B145; Thu, 18 Sep 2014 22:50:34 +0000 X-Env-Sender: roy.franz@linaro.org X-Msg-Ref: server-14.tower-31.messagelabs.com!1411080632!13006150!1 X-Originating-IP: [209.85.192.178] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 15125 invoked from network); 18 Sep 2014 22:50:33 -0000 Received: from mail-pd0-f178.google.com (HELO mail-pd0-f178.google.com) (209.85.192.178) by server-14.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 18 Sep 2014 22:50:33 -0000 Received: by mail-pd0-f178.google.com with SMTP id y10so117397pdj.9 for ; Thu, 18 Sep 2014 15:50:31 -0700 (PDT) X-Received: by 10.70.133.231 with SMTP id pf7mr11459202pdb.20.1411080631805; Thu, 18 Sep 2014 15:50:31 -0700 (PDT) Received: from rfranz-t520.swisscom.com (70-35-38-154.static.wiline.com. [70.35.38.154]) by mx.google.com with ESMTPSA id ig4sm66332pbb.55.2014.09.18.15.50.30 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 18 Sep 2014 15:50:31 -0700 (PDT) From: Roy Franz To: xen-devel@lists.xen.org, ian.campbell@citrix.com, stefano.stabellini@citrix.com, tim@xen.org, jbeulich@suse.com, keir@xen.org Date: Thu, 18 Sep 2014 15:50:04 -0700 Message-Id: <1411080607-32365-14-git-send-email-roy.franz@linaro.org> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1411080607-32365-1-git-send-email-roy.franz@linaro.org> References: <1411080607-32365-1-git-send-email-roy.franz@linaro.org> Cc: Roy Franz , fu.wei@linaro.org Subject: [Xen-devel] [PATCH V5 13/15] add arm64 cache flushing code from linux v3.16 X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: roy.franz@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: __flush_dcache_all added from arch/arm64/mm/cache.S, with helper macros from arch/arm64/include/asm/assembler.h, from v3.16. The cache flushing is required when transitioning from EFI code that runs with cache enable to Xen startup code which expects the cache to be disabled. Signed-off-by: Roy Franz Acked-by: Ian Campbell --- xen/arch/arm/arm64/Makefile | 1 + xen/arch/arm/arm64/cache.S | 100 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 101 insertions(+) create mode 100644 xen/arch/arm/arm64/cache.S diff --git a/xen/arch/arm/arm64/Makefile b/xen/arch/arm/arm64/Makefile index d2d5875..c7243f5 100644 --- a/xen/arch/arm/arm64/Makefile +++ b/xen/arch/arm/arm64/Makefile @@ -7,5 +7,6 @@ obj-y += domain.o obj-y += vfp.o obj-y += smpboot.o obj-y += domctl.o +obj-y += cache.o obj-$(EARLY_PRINTK) += debug.o diff --git a/xen/arch/arm/arm64/cache.S b/xen/arch/arm/arm64/cache.S new file mode 100644 index 0000000..fb6dff1 --- /dev/null +++ b/xen/arch/arm/arm64/cache.S @@ -0,0 +1,100 @@ +/* + * Cache maintenance + * + * Copyright (C) 2001 Deep Blue Solutions Ltd. + * Copyright (C) 2012 ARM Ltd. + * Copyright (C) 1996-2000 Russell King + * Copyright (C) 2012 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * Enable and disable interrupts. + */ + .macro disable_irq + msr daifset, #2 + .endm + + .macro enable_irq + msr daifclr, #2 + .endm + +/* + * Save/disable and restore interrupts. + */ + .macro save_and_disable_irqs, olddaif + mrs \olddaif, daif + disable_irq + .endm + + .macro restore_irqs, olddaif + msr daif, \olddaif + .endm + +/* + * __flush_dcache_all() + * + * Flush the whole D-cache. + * + * Corrupted registers: x0-x7, x9-x11 + */ + ENTRY(__flush_dcache_all) +__flush_dcache_all: + dmb sy // ensure ordering with previous memory accesses + mrs x0, clidr_el1 // read clidr + and x3, x0, #0x7000000 // extract loc from clidr + lsr x3, x3, #23 // left align loc bit field + cbz x3, finished // if loc is 0, then no need to clean + mov x10, #0 // start clean at cache level 0 +loop1: + add x2, x10, x10, lsr #1 // work out 3x current cache level + lsr x1, x0, x2 // extract cache type bits from clidr + and x1, x1, #7 // mask of the bits for current cache only + cmp x1, #2 // see what cache we have at this level + b.lt skip // skip if no cache, or just i-cache + save_and_disable_irqs x9 // make CSSELR and CCSIDR access atomic + msr csselr_el1, x10 // select current cache level in csselr + isb // isb to sych the new cssr&csidr + mrs x1, ccsidr_el1 // read the new ccsidr + restore_irqs x9 + and x2, x1, #7 // extract the length of the cache lines + add x2, x2, #4 // add 4 (line length offset) + mov x4, #0x3ff + and x4, x4, x1, lsr #3 // find maximum number on the way size + clz w5, w4 // find bit position of way size increment + mov x7, #0x7fff + and x7, x7, x1, lsr #13 // extract max number of the index size +loop2: + mov x9, x4 // create working copy of max way size +loop3: + lsl x6, x9, x5 + orr x11, x10, x6 // factor way and cache number into x11 + lsl x6, x7, x2 + orr x11, x11, x6 // factor index number into x11 + dc cisw, x11 // clean & invalidate by set/way + subs x9, x9, #1 // decrement the way + b.ge loop3 + subs x7, x7, #1 // decrement the index + b.ge loop2 +skip: + add x10, x10, #2 // increment cache number + cmp x3, x10 + b.gt loop1 +finished: + mov x10, #0 // swith back to cache level 0 + msr csselr_el1, x10 // select current cache level in csselr + dsb sy + isb + ret +ENDPROC(__flush_dcache_all)