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[50.57.142.19]) by mx.google.com with ESMTPS id h14si17409518qge.47.2014.10.20.10.02.46 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 20 Oct 2014 10:02:46 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XgGKI-0001VW-7l; Mon, 20 Oct 2014 17:00:58 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XgGKG-0001UC-47 for xen-devel@lists.xensource.com; Mon, 20 Oct 2014 17:00:56 +0000 Received: from [85.158.137.68:42369] by server-9.bemta-3.messagelabs.com id 6D/E4-30790-7CF35445; Mon, 20 Oct 2014 17:00:55 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-2.tower-31.messagelabs.com!1413824451!10924547!1 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.12.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 11233 invoked from network); 20 Oct 2014 17:00:54 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-2.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 20 Oct 2014 17:00:54 -0000 X-IronPort-AV: E=Sophos;i="5.04,757,1406592000"; d="scan'208";a="184250873" Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.78) with Microsoft SMTP Server id 14.3.181.6; Mon, 20 Oct 2014 13:00:48 -0400 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1XgGK2-0002Wv-RD; Mon, 20 Oct 2014 18:00:42 +0100 From: Stefano Stabellini To: Date: Mon, 20 Oct 2014 17:58:12 +0100 Message-ID: <1413824297-2805-3-git-send-email-stefano.stabellini@eu.citrix.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-DLP: MIA1 Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com, JBeulich@suse.com, Stefano Stabellini Subject: [Xen-devel] [PATCH v9 3/8] xen/arm: return int from *_dcache_va_range X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.169 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: These functions cannot really fail on ARM, but their x86 equivalents can (-EOPNOTSUPP). Change the prototype to return int. Signed-off-by: Stefano Stabellini Reviewed-by: Julien Grall --- Changes in v9: - remove useless ASSERT; - add a comment on ARM callers assuming that these functions cannot fail. Changes in v6: - do not return int from flush_page_to_ram. --- xen/include/asm-arm/page.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index fb1e710..69e9a61 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -268,16 +268,18 @@ extern size_t cacheline_bytes; /* Functions for flushing medium-sized areas. * if 'range' is large enough we might want to use model-specific * full-cache flushes. */ -static inline void clean_dcache_va_range(const void *p, unsigned long size) +static inline int clean_dcache_va_range(const void *p, unsigned long size) { const void *end; dsb(sy); /* So the CPU issues all writes to the range */ for ( end = p + size; p < end; p += cacheline_bytes ) asm volatile (__clean_dcache_one(0) : : "r" (p)); dsb(sy); /* So we know the flushes happen before continuing */ + /* ARM callers assume that dcache_* functions cannot fail. */ + return 0; } -static inline void clean_and_invalidate_dcache_va_range +static inline int clean_and_invalidate_dcache_va_range (const void *p, unsigned long size) { const void *end; @@ -285,6 +287,8 @@ static inline void clean_and_invalidate_dcache_va_range for ( end = p + size; p < end; p += cacheline_bytes ) asm volatile (__clean_and_invalidate_dcache_one(0) : : "r" (p)); dsb(sy); /* So we know the flushes happen before continuing */ + /* ARM callers assume that dcache_* functions cannot fail. */ + return 0; } /* Macros for flushing a single small item. The predicate is always