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[50.57.142.19]) by mx.google.com with ESMTPS id w9si28945191qcj.42.2014.11.03.02.19.31 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 03 Nov 2014 02:19:31 -0800 (PST) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XlEhr-0008K9-NM; Mon, 03 Nov 2014 10:17:51 +0000 Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XlEdV-00088C-G3 for xen-devel@lists.xen.org; Mon, 03 Nov 2014 10:13:21 +0000 Received: from [85.158.143.35] by server-2.bemta-4.messagelabs.com id 3F/9F-24532-04557545; Mon, 03 Nov 2014 10:13:20 +0000 X-Env-Sender: frediano.ziglio@huawei.com X-Msg-Ref: server-16.tower-21.messagelabs.com!1415009594!8898651!1 X-Originating-IP: [119.145.14.64] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTE5LjE0NS4xNC42NCA9PiA4MDE5MQ==\n X-StarScan-Received: X-StarScan-Version: 6.12.4; banners=-,-,- X-VirusChecked: Checked Received: (qmail 22126 invoked from network); 3 Nov 2014 10:13:17 -0000 Received: from szxga01-in.huawei.com (HELO szxga01-in.huawei.com) (119.145.14.64) by server-16.tower-21.messagelabs.com with RC4-SHA encrypted SMTP; 3 Nov 2014 10:13:17 -0000 Received: from 172.24.2.119 (EHLO szxeml403-hub.china.huawei.com) ([172.24.2.119]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CDW38062; Mon, 03 Nov 2014 18:13:13 +0800 (CST) Received: from localhost.localdomain (10.47.73.48) by szxeml403-hub.china.huawei.com (10.82.67.35) with Microsoft SMTP Server id 14.3.158.1; Mon, 3 Nov 2014 18:13:05 +0800 From: Frediano Ziglio To: Ian Campbell , Stefano Stabellini , Tim Deegan , Julien Grall , Date: Mon, 3 Nov 2014 10:11:56 +0000 Message-ID: <1415009522-6344-5-git-send-email-frediano.ziglio@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1415009522-6344-1-git-send-email-frediano.ziglio@huawei.com> References: <1415009522-6344-1-git-send-email-frediano.ziglio@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.73.48] X-CFilter-Loop: Reflected X-Mailman-Approved-At: Mon, 03 Nov 2014 10:17:48 +0000 Cc: zoltan.kiss@huawei.com, xen-devel@lists.xen.org Subject: [Xen-devel] [PATCH 04/10] xen/arm: Make gic-v2 code handle hip04-d01 platform X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: frediano.ziglio@huawei.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.54 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: The GIC in this platform is mainly compatible with the standard GICv2 beside: - ITARGET is extended to 16 bit to support 16 CPUs; - SGI mask is extended to support 16 CPUs; - maximum supported interrupt is 510. Signed-off-by: Frediano Ziglio Signed-off-by: Zoltan Kiss --- xen/arch/arm/gic-v2.c | 70 ++++++++++++++++++++++++++++++++++++++--------- xen/arch/arm/gic.c | 5 +++- xen/include/asm-arm/gic.h | 4 ++- 3 files changed, 64 insertions(+), 15 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index faad1ff..eef55ed 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -79,16 +79,22 @@ static struct gic_info gicv2_info; * logical CPU numbering. Let's use mapping as returned by the GIC * itself */ -static DEFINE_PER_CPU(u8, gic_cpu_id); +static DEFINE_PER_CPU(u16, gic_cpu_id); /* Maximum cpu interface per GIC */ -#define NR_GIC_CPU_IF 8 +static unsigned int nr_gic_cpu_if = 8; +static unsigned int gic_cpu_mask = 0xff; static inline void writeb_gicd(uint8_t val, unsigned int offset) { writeb_relaxed(val, gicv2.map_dbase + offset); } +static inline void writew_gicd(uint16_t val, unsigned int offset) +{ + writew_relaxed(val, gicv2.map_dbase + offset); +} + static inline void writel_gicd(uint32_t val, unsigned int offset) { writel_relaxed(val, gicv2.map_dbase + offset); @@ -132,7 +138,7 @@ static unsigned int gicv2_cpu_mask(const cpumask_t *cpumask) cpumask_and(&possible_mask, cpumask, &cpu_possible_map); for_each_cpu( cpu, &possible_mask ) { - ASSERT(cpu < NR_GIC_CPU_IF); + ASSERT(cpu < nr_gic_cpu_if); mask |= per_cpu(gic_cpu_id, cpu); } @@ -203,6 +209,15 @@ static unsigned int gicv2_read_irq(void) return (readl_gicc(GICC_IAR) & GICC_IA_IRQ); } +/* Set target CPU mask (RAZ/WI on uniprocessor) */ +static void gicv2_set_irq_mask(int irq, unsigned int mask) +{ + if ( platform_has_quirk(PLATFORM_QUIRK_GICV2_16_CPU) ) + writew_gicd(mask, GICD_ITARGETSR + irq * 2); + else + writeb_gicd(mask, GICD_ITARGETSR + irq); +} + /* * needs to be called with a valid cpu_mask, ie each cpu in the mask has * already called gic_cpu_init @@ -230,7 +245,7 @@ static void gicv2_set_irq_properties(struct irq_desc *desc, writel_gicd(cfg, GICD_ICFGR + (irq / 16) * 4); /* Set target CPU mask (RAZ/WI on uniprocessor) */ - writeb_gicd(mask, GICD_ITARGETSR + irq); + gicv2_set_irq_mask(irq, mask); /* Set priority */ writeb_gicd(priority, GICD_IPRIORITYR + irq); @@ -244,16 +259,22 @@ static void __init gicv2_dist_init(void) uint32_t gic_cpus; int i; - cpumask = readl_gicd(GICD_ITARGETSR) & 0xff; - cpumask |= cpumask << 8; - cpumask |= cpumask << 16; + cpumask = readl_gicd(GICD_ITARGETSR) & gic_cpu_mask; /* Disable the distributor */ writel_gicd(0, GICD_CTLR); type = readl_gicd(GICD_TYPER); gicv2_info.nr_lines = 32 * ((type & GICD_TYPE_LINES) + 1); - gic_cpus = 1 + ((type & GICD_TYPE_CPUS) >> 5); + if ( platform_has_quirk(PLATFORM_QUIRK_GICV2_16_CPU) ) + { + gic_cpus = 16; + BUG_ON( gicv2_info.nr_lines > 510 ); + } + else + { + gic_cpus = 1 + ((type & GICD_TYPE_CPUS) >> 5); + } printk("GICv2: %d lines, %d cpu%s%s (IID %8.8x).\n", gicv2_info.nr_lines, gic_cpus, (gic_cpus == 1) ? "" : "s", (type & GICD_TYPE_SEC) ? ", secure" : "", @@ -264,8 +285,19 @@ static void __init gicv2_dist_init(void) writel_gicd(0x0, GICD_ICFGR + (i / 16) * 4); /* Route all global IRQs to this CPU */ - for ( i = 32; i < gicv2_info.nr_lines; i += 4 ) - writel_gicd(cpumask, GICD_ITARGETSR + (i / 4) * 4); + if ( platform_has_quirk(PLATFORM_QUIRK_GICV2_16_CPU) ) + { + cpumask |= cpumask << 16; + for ( i = 32; i < gicv2_info.nr_lines; i += 2 ) + writel_gicd(cpumask, GICD_ITARGETSR + (i / 2) * 4); + } + else + { + cpumask |= cpumask << 8; + cpumask |= cpumask << 16; + for ( i = 32; i < gicv2_info.nr_lines; i += 4 ) + writel_gicd(cpumask, GICD_ITARGETSR + (i / 4) * 4); + } /* Default priority for global interrupts */ for ( i = 32; i < gicv2_info.nr_lines; i += 4 ) @@ -285,7 +317,7 @@ static void __cpuinit gicv2_cpu_init(void) { int i; - this_cpu(gic_cpu_id) = readl_gicd(GICD_ITARGETSR) & 0xff; + this_cpu(gic_cpu_id) = readl_gicd(GICD_ITARGETSR) & gic_cpu_mask; /* The first 32 interrupts (PPI and SGI) are banked per-cpu, so * even though they are controlled with GICD registers, they must @@ -348,6 +380,11 @@ static int gicv2_secondary_cpu_init(void) return 0; } +static inline unsigned gicd_sgi_target_shift(void) +{ + return 8 + 16 - nr_gic_cpu_if; +} + static void gicv2_send_SGI(enum gic_sgi sgi, enum gic_sgi_mode irqmode, const cpumask_t *cpu_mask) { @@ -366,7 +403,7 @@ static void gicv2_send_SGI(enum gic_sgi sgi, enum gic_sgi_mode irqmode, cpumask_and(&online_mask, cpu_mask, &cpu_online_map); mask = gicv2_cpu_mask(&online_mask); writel_gicd(GICD_SGI_TARGET_LIST | - (mask << GICD_SGI_TARGET_SHIFT) | sgi, + (mask << gicd_sgi_target_shift()) | sgi, GICD_SGIR); break; default: @@ -581,7 +618,7 @@ static void gicv2_irq_set_affinity(struct irq_desc *desc, const cpumask_t *cpu_m mask = gicv2_cpu_mask(cpu_mask); /* Set target CPU mask (RAZ/WI on uniprocessor) */ - writeb_gicd(mask, GICD_ITARGETSR + desc->irq); + gicv2_set_irq_mask(desc->irq, mask); spin_unlock(&gicv2.lock); } @@ -690,6 +727,12 @@ static int __init gicv2_init(struct dt_device_node *node, const void *data) dt_device_set_used_by(node, DOMID_XEN); + if ( platform_has_quirk(PLATFORM_QUIRK_GICV2_16_CPU) ) + { + nr_gic_cpu_if = 16; + gic_cpu_mask = 0xffff; + } + res = dt_device_get_address(node, 0, &gicv2.dbase, NULL); if ( res || !gicv2.dbase || (gicv2.dbase & ~PAGE_MASK) ) panic("GICv2: Cannot find a valid address for the distributor"); @@ -769,6 +812,7 @@ static const char * const gicv2_dt_compat[] __initconst = DT_COMPAT_GIC_CORTEX_A15, DT_COMPAT_GIC_CORTEX_A7, DT_COMPAT_GIC_400, + DT_COMPAT_GIC_HIP04, NULL }; diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 70d10d6..cd934cf 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -563,12 +563,15 @@ static void do_sgi(struct cpu_user_regs *regs, enum gic_sgi sgi) void gic_interrupt(struct cpu_user_regs *regs, int is_fiq) { unsigned int irq; + unsigned int max_irq = platform_has_quirk(PLATFORM_QUIRK_GICV2_16_CPU) ? + 510 : + 1021; do { /* Reading IRQ will ACK it */ irq = gic_hw_ops->read_irq(); - if ( likely(irq >= 16 && irq < 1021) ) + if ( likely(irq >= 16 && irq < max_irq) ) { local_irq_enable(); do_IRQ(regs, irq, is_fiq); diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 187dc46..5adb628 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -155,10 +155,12 @@ #define DT_COMPAT_GIC_400 "arm,gic-400" #define DT_COMPAT_GIC_CORTEX_A15 "arm,cortex-a15-gic" #define DT_COMPAT_GIC_CORTEX_A7 "arm,cortex-a7-gic" +#define DT_COMPAT_GIC_HIP04 "hisilicon,hip04-gic" #define DT_MATCH_GIC_V2 DT_MATCH_COMPATIBLE(DT_COMPAT_GIC_CORTEX_A15), \ DT_MATCH_COMPATIBLE(DT_COMPAT_GIC_CORTEX_A7), \ - DT_MATCH_COMPATIBLE(DT_COMPAT_GIC_400) + DT_MATCH_COMPATIBLE(DT_COMPAT_GIC_400), \ + DT_MATCH_COMPATIBLE(DT_COMPAT_GIC_HIP04) #define DT_COMPAT_GIC_V3 "arm,gic-v3"