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[50.57.142.19]) by mx.google.com with ESMTPS id eq1si39807513vdc.12.2015.04.29.02.40.24 (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 29 Apr 2015 02:40:24 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1YnOS6-0001It-QQ; Wed, 29 Apr 2015 09:38:46 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1YnOS5-0001Io-LU for xen-devel@lists.xen.org; Wed, 29 Apr 2015 09:38:45 +0000 Received: from [193.109.254.147] by server-1.bemta-14.messagelabs.com id B2/3B-09816-4A6A0455; Wed, 29 Apr 2015 09:38:44 +0000 X-Env-Sender: pranavkumar@linaro.org X-Msg-Ref: server-9.tower-27.messagelabs.com!1430300322!13145323!1 X-Originating-IP: [209.85.192.170] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 6.13.14; banners=-,-,- X-VirusChecked: Checked Received: (qmail 6331 invoked from network); 29 Apr 2015 09:38:43 -0000 Received: from mail-pd0-f170.google.com (HELO mail-pd0-f170.google.com) (209.85.192.170) by server-9.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 29 Apr 2015 09:38:43 -0000 Received: by pdbqd1 with SMTP id qd1so23335706pdb.2 for ; Wed, 29 Apr 2015 02:38:41 -0700 (PDT) X-Received: by 10.68.87.196 with SMTP id ba4mr28563082pbb.153.1430300321639; Wed, 29 Apr 2015 02:38:41 -0700 (PDT) Received: from pnqlab006.amcc.com ([182.73.239.130]) by mx.google.com with ESMTPSA id k4sm24895108pdk.7.2015.04.29.02.38.37 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 29 Apr 2015 02:38:40 -0700 (PDT) From: Pranavkumar Sawargaonkar To: xen-devel@lists.xen.org Date: Wed, 29 Apr 2015 15:08:27 +0530 Message-Id: <1430300307-10066-1-git-send-email-pranavkumar@linaro.org> X-Mailer: git-send-email 1.7.9.5 Cc: ian.campbell@citrix.com, patches@apm.com, julien.grall@citrix.com, stefano.stabellini@citrix.com, christoffer.dall@linaro.org, Pranavkumar Sawargaonkar Subject: [Xen-devel] [PATCH V3] xen: arm: X-Gene Storm check GIC DIST address for EOI quirk X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: pranavkumar@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.52 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: In old X-Gene Storm firmware and DT, secure mode addresses have been mentioned in GICv2 node. In this case maintenance interrupt is used instead of EOI HW method. This patch checks the GIC Distributor Base Address to enable EOI quirk for old firmware. Ref: http://lists.xen.org/archives/html/xen-devel/2014-07/msg01263.html Signed-off-by: Pranavkumar Sawargaonkar Tested-by: Christoffer Dall --- ChangeLog: V3: - Indentation fixes and other misc comments on V2. V2: - Fine tune interrupt controller node search as per comments on V1 patch - Incorporating other misc comments on V1. V1: - Initial patch. --- xen/arch/arm/platforms/xgene-storm.c | 40 +++++++++++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/platforms/xgene-storm.c b/xen/arch/arm/platforms/xgene-storm.c index 1812e5b..c717360 100644 --- a/xen/arch/arm/platforms/xgene-storm.c +++ b/xen/arch/arm/platforms/xgene-storm.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -35,9 +36,44 @@ static u64 reset_addr, reset_size; static u32 reset_mask; static bool reset_vals_valid = false; +#define XGENE_SEC_GICV2_DIST_ADDR 0x78010000 +static u32 __read_mostly xgene_quirks = PLATFORM_QUIRK_GIC_64K_STRIDE; + +static void __init xgene_check_pirq_eoi(void) +{ + const struct dt_device_node *node; + int res; + paddr_t dbase; + const struct dt_device_match xgene_dt_int_ctrl_match[] = + { + DT_MATCH_COMPATIBLE("arm,cortex-a15-gic"), + { /*sentinel*/ }, + }; + + node = dt_find_interrupt_controller(xgene_dt_int_ctrl_match); + if ( !node ) + panic("%s: Can not find interrupt controller node", __func__); + + res = dt_device_get_address(node, 0, &dbase, NULL); + if ( !dbase ) + panic("%s: Cannot find a valid address for the distributor", __func__); + + /* + * In old X-Gene Storm firmware and DT, secure mode addresses have + * been mentioned in GICv2 node. We have to use maintenance interrupt + * instead of EOI HW in this case. We check the GIC Distributor Base + * Address to maintain compatibility with older firmware. + */ + if ( dbase == XGENE_SEC_GICV2_DIST_ADDR ) + { + xgene_quirks |= PLATFORM_QUIRK_GUEST_PIRQ_NEED_EOI; + printk("Xen: WARNING: OLD X-Gene Firmware, disabling PIRQ EOI mode\n"); + } +} + static uint32_t xgene_storm_quirks(void) { - return PLATFORM_QUIRK_GIC_64K_STRIDE|PLATFORM_QUIRK_GUEST_PIRQ_NEED_EOI; + return xgene_quirks; } static int map_one_mmio(struct domain *d, const char *what, @@ -216,6 +252,8 @@ static int xgene_storm_init(void) reset_mask = XGENE_RESET_MASK; reset_vals_valid = true; + xgene_check_pirq_eoi(); + return 0; }