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[50.57.142.19]) by mx.google.com with ESMTPS id qa9si8699942vdb.18.2015.05.17.13.06.15 (version=TLSv1 cipher=RC4-SHA bits=128/128); Sun, 17 May 2015 13:06:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Yu4oS-0001zI-4I; Sun, 17 May 2015 20:05:28 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Yu4oR-0001xb-87 for xen-devel@lists.xen.org; Sun, 17 May 2015 20:05:27 +0000 Received: from [193.109.254.147] by server-10.bemta-14.messagelabs.com id DE/E5-02785-684F8555; Sun, 17 May 2015 20:05:26 +0000 X-Env-Sender: parth.dixit@linaro.org X-Msg-Ref: server-15.tower-27.messagelabs.com!1431893123!18256769!1 X-Originating-IP: [209.85.192.182] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 6.13.15; banners=-,-,- X-VirusChecked: Checked Received: (qmail 31314 invoked from network); 17 May 2015 20:05:25 -0000 Received: from mail-pd0-f182.google.com (HELO mail-pd0-f182.google.com) (209.85.192.182) by server-15.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 17 May 2015 20:05:25 -0000 Received: by pdea3 with SMTP id a3so116254513pde.2 for ; Sun, 17 May 2015 13:05:23 -0700 (PDT) X-Received: by 10.70.103.200 with SMTP id fy8mr37633717pdb.136.1431893123506; Sun, 17 May 2015 13:05:23 -0700 (PDT) Received: from localhost.localdomain ([117.247.24.139]) by mx.google.com with ESMTPSA id j9sm7838401pdm.53.2015.05.17.13.05.19 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 May 2015 13:05:22 -0700 (PDT) From: Parth Dixit To: xen-devel@lists.xen.org Date: Mon, 18 May 2015 01:33:42 +0530 Message-Id: <1431893048-5214-16-git-send-email-parth.dixit@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1431893048-5214-1-git-send-email-parth.dixit@linaro.org> References: <1431893048-5214-1-git-send-email-parth.dixit@linaro.org> Cc: keir@xen.org, ian.campbell@citrix.com, andrew.cooper3@citrix.com, tim@xen.org, julien.grall@citrix.com, stefano.stabellini@citrix.com, jbeulich@suse.com, parth.dixit@linaro.org, christoffer.dall@linaro.org Subject: [Xen-devel] [PATCH v2 15/41] arm : acpi parse GTDT to initialize timer X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: parth.dixit@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.52 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: Parse GTDT (Generic Timer Descriptor Table) to initialize timer. Using the information presented by GTDT to initialize the arch timer (not memory-mapped). Clear all el2 fields in GTDT table after initialization for passing it to Dom0. Signed-off-by: Naresh Bhat Signed-off-by: Parth Dixit --- xen/arch/arm/acpi/boot.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/time.c | 38 +++++++++++++++++++++++++---------- xen/include/asm-arm/acpi.h | 2 ++ 3 files changed, 79 insertions(+), 11 deletions(-) diff --git a/xen/arch/arm/acpi/boot.c b/xen/arch/arm/acpi/boot.c index 7d9758f..a8311ae 100644 --- a/xen/arch/arm/acpi/boot.c +++ b/xen/arch/arm/acpi/boot.c @@ -30,6 +30,8 @@ #include #include +#include +#include /* Processors with enabled flag and sane MPIDR */ static int enabled_cpus; @@ -40,6 +42,54 @@ static bool_t __initdata bootcpu_valid; /* arch-optional setting to enable display of offline cpus >= nr_cpu_ids */ static unsigned int total_cpus = 0; +/* Initialize per-processor generic timer */ +void __init acpi_preinit_xen_time(unsigned int generic_timer_irq[]) +{ + int type; + struct acpi_table_gtdt *gtdt=NULL; + u8 checksum; + static const int GTDT_INTRL_TAB[] = + { + ACPI_IRQ_TYPE_LEVEL_HIGH, + ACPI_IRQ_TYPE_EDGE_RISING, + ACPI_IRQ_TYPE_LEVEL_LOW, + ACPI_IRQ_TYPE_EDGE_FALLING + }; + + acpi_get_table(ACPI_SIG_GTDT, 0, (struct acpi_table_header **)>dt); + + if( gtdt ) + { + /* Initialize all the generic timer IRQ variable from GTDT table */ + + type = GTDT_INTRL_TAB[gtdt->non_secure_el1_flags & ACPI_GTDT_INTR_MASK]; + set_irq_type(gtdt->non_secure_el1_interrupt, type); + generic_timer_irq[TIMER_PHYS_NONSECURE_PPI] = + gtdt->non_secure_el1_interrupt; + + type = GTDT_INTRL_TAB[gtdt->secure_el1_flags & ACPI_GTDT_INTR_MASK]; + set_irq_type(gtdt->secure_el1_interrupt, type); + generic_timer_irq[TIMER_PHYS_SECURE_PPI] = + gtdt->secure_el1_interrupt; + + type = GTDT_INTRL_TAB[gtdt->non_secure_el2_flags & ACPI_GTDT_INTR_MASK]; + set_irq_type(gtdt->non_secure_el2_interrupt, type); + generic_timer_irq[TIMER_HYP_PPI] = + gtdt->non_secure_el2_interrupt; + + type = GTDT_INTRL_TAB[gtdt->virtual_timer_flags & ACPI_GTDT_INTR_MASK]; + set_irq_type(gtdt->virtual_timer_interrupt, type); + generic_timer_irq[TIMER_VIRT_PPI] = + gtdt->virtual_timer_interrupt; + + gtdt->non_secure_el2_interrupt = 0; + gtdt->non_secure_el2_flags = 0; + checksum = acpi_tb_checksum(ACPI_CAST_PTR(u8, gtdt), gtdt->header.length); + gtdt->header.checksum -= checksum; + clean_dcache_va_range(gtdt, sizeof(struct acpi_table_gtdt)); + } +} + /* * acpi_map_gic_cpu_interface - generates a logical cpu number * and map to MPIDR represented by GICC structure diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c index ce6d3fd..bff95ab 100644 --- a/xen/arch/arm/time.c +++ b/xen/arch/arm/time.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -64,7 +65,7 @@ unsigned int timer_get_irq(enum timer_ppi ppi) static __initdata struct dt_device_node *timer; /* Set up the timer on the boot CPU (early init function) */ -void __init preinit_xen_time(void) +static void __init dt_preinit_xen_time(void) { static const struct dt_device_match timer_ids[] __initconst = { @@ -72,7 +73,6 @@ void __init preinit_xen_time(void) { /* sentinel */ }, }; int res; - u32 rate; timer = dt_find_matching_node(NULL, timer_ids); if ( !timer ) @@ -84,8 +84,21 @@ void __init preinit_xen_time(void) if ( res ) panic("Timer: Cannot initialize platform timer"); - res = dt_property_read_u32(timer, "clock-frequency", &rate); - if ( res ) +} + + + +void __init preinit_xen_time(void) +{ + u32 rate; + + /* Initialize all the generic timers presented in GTDT */ + if ( acpi_disabled ) + dt_preinit_xen_time(); + else + acpi_preinit_xen_time(timer_irq); + + if( acpi_disabled && dt_property_read_u32(timer, "clock-frequency", &rate) ) cpu_khz = rate / 1000; else cpu_khz = READ_SYSREG32(CNTFRQ_EL0) / 1000; @@ -99,14 +112,17 @@ int __init init_xen_time(void) int res; unsigned int i; - /* Retrieve all IRQs for the timer */ - for ( i = TIMER_PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++ ) + if( acpi_disabled ) { - res = platform_get_irq(timer, i); - - if ( res < 0 ) - panic("Timer: Unable to retrieve IRQ %u from the device tree", i); - timer_irq[i] = res; + /* Retrieve all IRQs for the timer */ + for ( i = TIMER_PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++ ) + { + res = platform_get_irq(timer, i); + + if ( res < 0 ) + panic("Timer: Unable to retrieve IRQ %u from the device tree", i); + timer_irq[i] = res; + } } /* Check that this CPU supports the Generic Timer interface */ diff --git a/xen/include/asm-arm/acpi.h b/xen/include/asm-arm/acpi.h index 1767143..482cc5b 100644 --- a/xen/include/asm-arm/acpi.h +++ b/xen/include/asm-arm/acpi.h @@ -36,10 +36,12 @@ bool_t acpi_psci_present(void); /* 1 to indicate HVC is present instead of SMC as the PSCI conduit */ bool_t acpi_psci_hvc_present(void); void __init acpi_init_cpus(void); +void __init acpi_preinit_xen_time(unsigned int generic_timer_irq[]); #else static inline bool_t acpi_psci_present(void) { return false; } static inline bool_t acpi_psci_hvc_present(void) {return false; } static inline void acpi_init_cpus(void) { } +static inline void acpi_preinit_xen_time(unsigned int generic_timer_irq[]){ } #endif /* CONFIG_ACPI */ /* Basic configuration for ACPI */