From patchwork Wed Mar 16 07:18:36 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Green X-Patchwork-Id: 623 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:44:10 -0000 Delivered-To: patches@linaro.org Received: by 10.151.46.5 with SMTP id y5cs1256ybj; Wed, 16 Mar 2011 00:18:39 -0700 (PDT) Received: by 10.216.3.3 with SMTP id 3mr4680841weg.57.1300259919178; Wed, 16 Mar 2011 00:18:39 -0700 (PDT) Received: from mail-ww0-f50.google.com (mail-ww0-f50.google.com [74.125.82.50]) by mx.google.com with ESMTPS id r15si1151338wec.102.2011.03.16.00.18.38 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 16 Mar 2011 00:18:39 -0700 (PDT) Received-SPF: pass (google.com: domain of andy.warmcat.com@googlemail.com designates 74.125.82.50 as permitted sender) client-ip=74.125.82.50; Authentication-Results: mx.google.com; spf=pass (google.com: domain of andy.warmcat.com@googlemail.com designates 74.125.82.50 as permitted sender) smtp.mail=andy.warmcat.com@googlemail.com; dkim=pass (test mode) header.i=@googlemail.com Received: by mail-ww0-f50.google.com with SMTP id 33so1741876wwc.31 for ; Wed, 16 Mar 2011 00:18:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:sender:from:subject:to:cc:date:message-id :in-reply-to:references:user-agent:mime-version:content-type :content-transfer-encoding; bh=WHdTIySwPqc75DnPyLFmTpLKflKbCt9U02eeCITVZMI=; b=tGDQjjTInAcjd4FPtUoRzQz1ulb4JbeKIUMas4kOJCln3VYKHudeL5/uD2WCh6xE7+ EifOKwEXVz1d91jDf3CCFwZD2wUxMqdpUjj+m8zXckU9zsP4UQWvbIDEwIutBd7gSUnl EY4hYvQizJlFBqa5FqNpg6LJf0r3wmOIx8n2k= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=sender:from:subject:to:cc:date:message-id:in-reply-to:references :user-agent:mime-version:content-type:content-transfer-encoding; b=Y/PsaxfPIzlz+8zqCwrg40MnmPwUJI2Rv5Ggc/izm9/dq4yLVWm9AqMrvFZfOH1FjW zo7mztLua199JKvYyDpPCwrZ9oI1AnwplqMytot+htJ3pls0g3w+FvIu4V4/wXSTYdEM Axhde+XW0x/5tPxVET1z6ODD+PSBC1pohqHyw= Received: by 10.216.82.77 with SMTP id n55mr406211wee.52.1300259918330; Wed, 16 Mar 2011 00:18:38 -0700 (PDT) Received: from otae.warmcat.com (cpc1-nrte21-2-0-cust677.8-4.cable.virginmedia.com [81.111.78.166]) by mx.google.com with ESMTPS id n2sm368091wej.22.2011.03.16.00.18.37 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 16 Mar 2011 00:18:37 -0700 (PDT) Sender: Andy Green From: Andy Green Subject: [PATCH 3 02/18] I2C: OMAP2+: Name registers in I2C IP V2 only accordingly To: linux-i2c@lists.infradead.org Cc: patches@linaro.org, Ben Dooks , Andy Green Date: Wed, 16 Mar 2011 07:18:36 +0000 Message-ID: <20110316071836.453.16452.stgit@otae.warmcat.com> In-Reply-To: <20110316071633.453.22228.stgit@otae.warmcat.com> References: <20110316071633.453.22228.stgit@otae.warmcat.com> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 The OMAP I2C driver dynamically chooses between two register sets of differing sizes depending on the cpu type it finds itself on. It has been observed that the existing code references non-existing registers on OMAP3530, because while it correctly chose the smaller register layout based on cpu type, the code uses the probed register ID to decide if to execute code referencing an extra register, and both register layout devices on OMAP3530 and OMAP4430 report the same probed ID of 0x40. This patch changes the extended register names only found on IP V2 of the I2C peripheral unit accordingly to help show up errors in usage. Cc: patches@linaro.org Cc: Ben Dooks Reported-by: Peter Maydell Signed-off-by: Andy Green --- drivers/i2c/busses/i2c-omap.c | 23 ++++++++++++----------- 1 files changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index 829a2a1..2826c13 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c @@ -72,11 +72,12 @@ enum { OMAP_I2C_SCLH_REG, OMAP_I2C_SYSTEST_REG, OMAP_I2C_BUFSTAT_REG, - OMAP_I2C_REVNB_LO, - OMAP_I2C_REVNB_HI, - OMAP_I2C_IRQSTATUS_RAW, - OMAP_I2C_IRQENABLE_SET, - OMAP_I2C_IRQENABLE_CLR, + /* only on OMAP4430 */ + OMAP_I2C_IP_V2_REVNB_LO, + OMAP_I2C_IP_V2_REVNB_HI, + OMAP_I2C_IP_V2_IRQSTATUS_RAW, + OMAP_I2C_IP_V2_IRQENABLE_SET, + OMAP_I2C_IP_V2_IRQENABLE_CLR, }; /* I2C Interrupt Enable Register (OMAP_I2C_IE): */ @@ -244,11 +245,11 @@ const static u8 omap4_reg_map[] = { [OMAP_I2C_SCLH_REG] = 0xb8, [OMAP_I2C_SYSTEST_REG] = 0xbC, [OMAP_I2C_BUFSTAT_REG] = 0xc0, - [OMAP_I2C_REVNB_LO] = 0x00, - [OMAP_I2C_REVNB_HI] = 0x04, - [OMAP_I2C_IRQSTATUS_RAW] = 0x24, - [OMAP_I2C_IRQENABLE_SET] = 0x2c, - [OMAP_I2C_IRQENABLE_CLR] = 0x30, + [OMAP_I2C_IP_V2_REVNB_LO] = 0x00, + [OMAP_I2C_IP_V2_REVNB_HI] = 0x04, + [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24, + [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c, + [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30, }; static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev, @@ -309,7 +310,7 @@ static void omap_i2c_idle(struct omap_i2c_dev *dev) dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); if (dev->rev >= OMAP_I2C_REV_ON_4430) - omap_i2c_write_reg(dev, OMAP_I2C_IRQENABLE_CLR, 1); + omap_i2c_write_reg(dev, OMAP_I2C_IP_V2_IRQENABLE_CLR, 1); else omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);