From patchwork Fri Sep 20 15:03:37 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 20479 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-yh0-f71.google.com (mail-yh0-f71.google.com [209.85.213.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 305B723906 for ; Fri, 20 Sep 2013 15:03:43 +0000 (UTC) Received: by mail-yh0-f71.google.com with SMTP id a41sf466250yho.6 for ; Fri, 20 Sep 2013 08:03:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:message-id:date:from:user-agent :mime-version:to:cc:subject:references:in-reply-to:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe:content-type :content-transfer-encoding; bh=JEWjjR5nLhky9/b1am/dIVIhazVnPlzo2Vc47EhyV8M=; b=dRuh10Jyf9mQ2L0LHYSePHknU9ghbBGPTsXaRCGvhS0blWRJqZW/MzBKRCWuW4fza3 pYor+BNfRnpmRh73qcVMAt893Cte07QIF3BDVE+MrGoQ05t51uW6axBzo12dot8G6/2x c3bG/Xs8kNyHHBGdZEcIs3+pHUNmx5N3sY3JjUVf85/iklFCSJI1yOYZtRNpqP+9LY4c gszsADCJws7yDym6zUfL3pBhGJ/CK/HqKUZizfWYQAvOU/qqWSJOxto1uOXAK7HWGulx poYM0lBOi7xA2TiNmDcsIb/leJaJIgt8JuhK08NNhNArTNG8suEpvAe1qRxRKf8tZ8G0 uGzg== X-Gm-Message-State: ALoCoQkvl3OFJ8k3ORdBm/3cghv9wzxyipuKttVLqD6fmdNWRzTZJpwrkaBfbTjNxCOhGREnoNH6 X-Received: by 10.224.51.68 with SMTP id c4mr2521463qag.7.1379689422991; Fri, 20 Sep 2013 08:03:42 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.81.230 with SMTP id d6ls294304qey.93.gmail; Fri, 20 Sep 2013 08:03:42 -0700 (PDT) X-Received: by 10.52.75.228 with SMTP id f4mr5546806vdw.6.1379689422922; Fri, 20 Sep 2013 08:03:42 -0700 (PDT) Received: from mail-vb0-f53.google.com (mail-vb0-f53.google.com [209.85.212.53]) by mx.google.com with ESMTPS id w20si3096535vco.143.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 20 Sep 2013 08:03:42 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.212.53 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.212.53; Received: by mail-vb0-f53.google.com with SMTP id i3so370722vbh.26 for ; Fri, 20 Sep 2013 08:03:42 -0700 (PDT) X-Received: by 10.221.27.73 with SMTP id rp9mr716001vcb.29.1379689420867; Fri, 20 Sep 2013 08:03:40 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp22876vcz; Fri, 20 Sep 2013 08:03:40 -0700 (PDT) X-Received: by 10.180.74.164 with SMTP id u4mr3112895wiv.17.1379689419572; Fri, 20 Sep 2013 08:03:39 -0700 (PDT) Received: from mail-wg0-f50.google.com (mail-wg0-f50.google.com [74.125.82.50]) by mx.google.com with ESMTPS id x3si5135845wje.78.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 20 Sep 2013 08:03:39 -0700 (PDT) Received-SPF: neutral (google.com: 74.125.82.50 is neither permitted nor denied by best guess record for domain of julien.grall@linaro.org) client-ip=74.125.82.50; Received: by mail-wg0-f50.google.com with SMTP id f12so629884wgh.17 for ; Fri, 20 Sep 2013 08:03:39 -0700 (PDT) X-Received: by 10.195.13.164 with SMTP id ez4mr6474678wjd.11.1379689419032; Fri, 20 Sep 2013 08:03:39 -0700 (PDT) Received: from [10.80.2.139] ([185.25.64.249]) by mx.google.com with ESMTPSA id fb9sm5538044wid.7.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 20 Sep 2013 08:03:38 -0700 (PDT) Message-ID: <523C63C9.1040708@linaro.org> Date: Fri, 20 Sep 2013 16:03:37 +0100 From: Julien Grall User-Agent: Mozilla/5.0 (X11; Linux i686; rv:17.0) Gecko/20130828 Icedove/17.0.8 MIME-Version: 1.0 To: ian.campbell@citrix.com CC: xen-devel@lists.xen.org, stefano.stabellini@eu.citrix.com, patches@linaro.org Subject: Re: [PATCH v3 3/6] xen/arm: gic: Use the correct CPU ID References: <1379510122-9467-1-git-send-email-julien.grall@linaro.org> <1379510122-9467-4-git-send-email-julien.grall@linaro.org> In-Reply-To: <1379510122-9467-4-git-send-email-julien.grall@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.53 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , I only resend this patch. ==================================================================================== commit 89aafa2d3d8a4f9ebce700673f89c8b4822a02e8 Author: Julien Grall Date: Thu Aug 29 18:38:06 2013 +0100 xen/arm: gic: Use the correct CPU ID The GIC mapping of CPU interfaces does not necessarily match the logical CPU numbering. When Xen wants to send an SGI to specific CPU, it needs to use the GIC CPU ID. It can be retrieved from ITARGETSR0, in fact when this field is read, the GIC will return a value that corresponds only to the processor reading the register. So Xen can use the PPI 0 to initialize the mapping. Signed-off-by: Julien Grall --- Changes in v4: - Make logical and between the cpumask given in arguments and cpu_possible_map. - Make sure the per_cpu is initialized - Add comment restriction for gic_set_irq_properties Changes in v3: - Correctly create the mask in gic_cpu_mask Changes in v2: - Use per-cpu variable instead of an array - Add comment for NR_GIC_CPU_IF diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index b969d23..9f703a0 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -57,6 +57,32 @@ static DEFINE_PER_CPU(uint64_t, lr_mask); static unsigned nr_lrs; +/* The GIC mapping of CPU interfaces does not necessarily match the + * logical CPU numbering. Let's use mapping as returned by the GIC + * itself + */ +static DEFINE_PER_CPU(u8, gic_cpu_id); + +/* Maximum cpu interface per GIC */ +#define NR_GIC_CPU_IF 8 + +static unsigned int gic_cpu_mask(const cpumask_t *cpumask) +{ + unsigned int cpu; + unsigned int mask = 0; + cpumask_t possible_mask; + + cpumask_and(&possible_mask, cpumask, &cpu_possible_map); + for_each_cpu(cpu, &possible_mask) + { + ASSERT(cpu < NR_GIC_CPU_IF); + ASSERT(__per_cpu_offset[cpu] != -(long)__per_cpu_start); + mask |= per_cpu(gic_cpu_id, cpu); + } + + return mask; +} + unsigned int gic_number_lines(void) { return gic.lines; @@ -182,16 +208,18 @@ static hw_irq_controller gic_guest_irq_type = { .set_affinity = gic_irq_set_affinity, }; -/* needs to be called with gic.lock held */ +/* + * - needs to be called with gic.lock held + * - needs to be called with a valid cpu_mask, ie each cpu in the mask has + * already called gic_cpu_init + */ static void gic_set_irq_properties(unsigned int irq, bool_t level, const cpumask_t *cpu_mask, unsigned int priority) { volatile unsigned char *bytereg; uint32_t cfg, edgebit; - unsigned int mask = cpumask_bits(cpu_mask)[0]; - - ASSERT(!(mask & ~0xff)); /* Target bitmap only support 8 CPUS */ + unsigned int mask = gic_cpu_mask(cpu_mask); /* Set edge / level */ cfg = GICD[GICD_ICFGR + irq / 16]; @@ -300,6 +328,8 @@ static void __cpuinit gic_cpu_init(void) { int i; + this_cpu(gic_cpu_id) = GICD[GICD_ITARGETSR] & 0xff; + /* The first 32 interrupts (PPI and SGI) are banked per-cpu, so * even though they are controlled with GICD registers, they must * be set up here with the other per-cpu state. */ @@ -431,13 +461,13 @@ void __init gic_init(void) void send_SGI_mask(const cpumask_t *cpumask, enum gic_sgi sgi) { - unsigned long mask = cpumask_bits(cpumask)[0]; + unsigned int mask = 0; + cpumask_t online_mask; ASSERT(sgi < 16); /* There are only 16 SGIs */ - mask &= cpumask_bits(&cpu_online_map)[0]; - - ASSERT(mask < 0x100); /* The target bitmap only supports 8 CPUs */ + cpumask_and(&online_mask, cpumask, &cpu_online_map); + mask = gic_cpu_mask(&online_mask); dsb();