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[50.57.142.19]) by mx.google.com with ESMTPS id v8si1938260qab.71.2014.11.19.06.08.03 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 19 Nov 2014 06:08:03 -0800 (PST) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Xr5tV-0006x6-Hi; Wed, 19 Nov 2014 14:06:05 +0000 Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Xr5tR-0006wr-Mt for xen-devel@lists.xen.org; Wed, 19 Nov 2014 14:06:04 +0000 Received: from [85.158.143.35] by server-3.bemta-4.messagelabs.com id 1D/EA-09936-8C3AC645; Wed, 19 Nov 2014 14:06:00 +0000 X-Env-Sender: julien.grall@linaro.org X-Msg-Ref: server-9.tower-21.messagelabs.com!1416405960!13937696!1 X-Originating-IP: [74.125.82.47] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 6.12.4; banners=-,-,- X-VirusChecked: Checked Received: (qmail 23370 invoked from network); 19 Nov 2014 14:06:00 -0000 Received: from mail-wg0-f47.google.com (HELO mail-wg0-f47.google.com) (74.125.82.47) by server-9.tower-21.messagelabs.com with RC4-SHA encrypted SMTP; 19 Nov 2014 14:06:00 -0000 Received: by mail-wg0-f47.google.com with SMTP id n12so945389wgh.20 for ; Wed, 19 Nov 2014 06:06:00 -0800 (PST) X-Received: by 10.180.75.116 with SMTP id b20mr13531115wiw.49.1416405960098; Wed, 19 Nov 2014 06:06:00 -0800 (PST) Received: from [10.80.2.139] ([185.25.64.249]) by mx.google.com with ESMTPSA id he3sm2442351wjc.15.2014.11.19.06.05.58 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Nov 2014 06:05:59 -0800 (PST) Message-ID: <546CA3C6.6010406@linaro.org> Date: Wed, 19 Nov 2014 14:05:58 +0000 From: Julien Grall User-Agent: Mozilla/5.0 (X11; Linux i686; rv:31.0) Gecko/20100101 Icedove/31.2.0 MIME-Version: 1.0 To: Andrii Tseglytskyi References: <1416399227.29243.33.camel@citrix.com> <546C8BD9.8090406@linaro.org> <546C9A88.6000100@linaro.org> In-Reply-To: Cc: "xen-devel@lists.xen.org" , Ian Campbell , Stefano Stabellini Subject: Re: [Xen-devel] Xen 4.5 random freeze question X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: On 11/19/2014 01:30 PM, Andrii Tseglytskyi wrote: > On Wed, Nov 19, 2014 at 3:26 PM, Julien Grall wrote: >> On 11/19/2014 12:40 PM, Andrii Tseglytskyi wrote: >>> Hi Julien, >>> >>> On Wed, Nov 19, 2014 at 2:23 PM, Julien Grall wrote: >>>> On 11/19/2014 12:17 PM, Stefano Stabellini wrote: >>>>> On Wed, 19 Nov 2014, Ian Campbell wrote: >>>>>> On Wed, 2014-11-19 at 11:42 +0000, Stefano Stabellini wrote: >>>>>>> So it looks like there is not actually anything wrong, is just that you >>>>>>> have too much inflight irqs? It should cause problems because in that >>>>>>> case GICH_HCR_UIE should be set and you should get a maintenance >>>>>>> interrupt when LRs become available (actually when "none, or only one, >>>>>>> of the List register entries is marked as a valid interrupt"). >>>>>>> >>>>>>> Maybe GICH_HCR_UIE is the one that doesn't work properly. >>>>>> >>>>>> How much testing did this aspect get when the no-maint-irq series >>>>>> originally went in? Did you manage to find a workload which filled all >>>>>> the LRs or try artificially limiting the number of LRs somehow in order >>>>>> to provoke it? >>>>>> >>>>>> I ask because my intuition is that this won't happen very much, meaning >>>>>> those code paths may not be as well tested... >>>>> >>>>> I did test it by artificially limiting the number of LRs to 1. >>>>> However there have been many iterations of that series and I didn't run >>>>> this test at every iteration. >>>> >>>> am I the only to think this may not be related to this bug? All the LRs >>>> are full with IRQ of the same priority. So it's valid. >>>> >>>> As gic_restore_pending_irqs is called every time that we return to the >>>> guest. It could be anything else. >>>> >>>> It would be interesting to see why we are trapping all the time in Xen. >>>> >>> >>> I may perform any test if you have some specific scenario. >> >> I have no specific scenario in my mind :/. >> >> It looks like I'm able to reproduce it on my ARM board by the restricted >> the number of LRs to 1. >> > > Do you mean that you got a hang with current xen/master branch ? Yes but I forgot to update another part of the code. With the patch below to restrict the number of LRs I'm still able to boot. And don't see any maintenance interrupt. Stefano, is it valid? diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index faad1ff..c1c0f7ff 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -327,6 +327,7 @@ static void __cpuinit gicv2_hyp_init(void) vtr = readl_gich(GICH_VTR); nr_lrs = (vtr & GICH_V2_VTR_NRLRGS) + 1; gicv2_info.nr_lrs = nr_lrs; + gicv2_info.nr_lrs = 1; writel_gich(GICH_MISR_EOI, GICH_MISR); } @@ -488,6 +489,16 @@ static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) static void gicv2_hcr_status(uint32_t flag, bool_t status) { + uint32_t lr = readl_gich(GICH_LR + 0); + + if ( status ) + lr |= GICH_V2_LR_MAINTENANCE_IRQ; + else + lr &= ~GICH_V2_LR_MAINTENANCE_IRQ; + + writel_gich(lr, GICH_LR + 0); + +#if 0 uint32_t hcr = readl_gich(GICH_HCR); if ( status ) @@ -496,6 +507,7 @@ static void gicv2_hcr_status(uint32_t flag, bool_t status) hcr &= (~flag); writel_gich(hcr, GICH_HCR); +#endif } static unsigned int gicv2_read_vmcr_priority(void) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 70d10d6..c726d7a 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -599,6 +599,7 @@ static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *r * on return to guest that is going to clear the old LRs and inject * new interrupts. */ + gdprintk(XENLOG_DEBUG, "\n"); } void gic_dump_info(struct vcpu *v)