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[50.57.142.19]) by mx.google.com with ESMTPS id r2si26714813vda.63.2014.11.18.07.42.20 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 18 Nov 2014 07:42:20 -0800 (PST) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XqktZ-0003Gp-HC; Tue, 18 Nov 2014 15:40:45 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XqktW-0003Gf-R8 for xen-devel@lists.xen.org; Tue, 18 Nov 2014 15:40:44 +0000 Received: from [85.158.137.68] by server-4.bemta-3.messagelabs.com id E3/A0-23865-A786B645; Tue, 18 Nov 2014 15:40:42 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-4.tower-31.messagelabs.com!1416325237!12152860!1 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.12.4; banners=-,-,- X-VirusChecked: Checked Received: (qmail 5132 invoked from network); 18 Nov 2014 15:40:40 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-4.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 18 Nov 2014 15:40:40 -0000 X-IronPort-AV: E=Sophos;i="5.07,410,1413244800"; d="scan'208";a="194022179" Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.78) with Microsoft SMTP Server id 14.3.181.6; Tue, 18 Nov 2014 10:40:18 -0500 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1Xqkt8-0006ZL-2U; Tue, 18 Nov 2014 15:40:18 +0000 Date: Tue, 18 Nov 2014 15:39:58 +0000 From: Stefano Stabellini X-X-Sender: sstabellini@kaball.uk.xensource.com To: Andrii Tseglytskyi In-Reply-To: Message-ID: References: <54662F69.8060700@linaro.org> User-Agent: Alpine 2.02 (DEB 1266 2009-07-14) MIME-Version: 1.0 X-DLP: MIA1 Cc: Julien Grall , "xen-devel@lists.xen.org" , Ian Campbell , Stefano Stabellini Subject: Re: [Xen-devel] Xen 4.5 random freeze question X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 74.125.82.50 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: On Tue, 18 Nov 2014, Andrii Tseglytskyi wrote: > OK, I see that GICH_V2_LR_MAINTENANCE_IRQ must always be set and > everything works fine > The following 2 patches fixes xen/master for my platform. > > Stefano, could you please take a look to these changes? > > commit 3628a0aa35706a8f532af865ed784536ce514eca > Author: Andrii Tseglytskyi > Date: Tue Nov 18 14:20:42 2014 +0200 > > xen/arm: dra7: always set GICH_V2_LR_MAINTENANCE_IRQ flag > > Change-Id: Ia380b3507a182b11592588f65fd23693d4f87434 > Signed-off-by: Andrii Tseglytskyi > > diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c > index 31fb81a..093ecdb 100644 > --- a/xen/arch/arm/gic-v2.c > +++ b/xen/arch/arm/gic-v2.c > @@ -396,13 +396,14 @@ static void gicv2_update_lr(int lr, const struct > pending_irq *p, > << GICH_V2_LR_PRIORITY_SHIFT) | > ((p->irq & GICH_V2_LR_VIRTUAL_MASK) << > GICH_V2_LR_VIRTUAL_SHIFT)); > > - if ( p->desc != NULL ) > + if ( platform_has_quirk(PLATFORM_QUIRK_GUEST_PIRQ_NEED_EOI) ) > { > - if ( platform_has_quirk(PLATFORM_QUIRK_GUEST_PIRQ_NEED_EOI) ) > - lr_reg |= GICH_V2_LR_MAINTENANCE_IRQ; > - else > - lr_reg |= GICH_V2_LR_HW | ((p->desc->irq & > GICH_V2_LR_PHYSICAL_MASK ) > - << GICH_V2_LR_PHYSICAL_SHIFT); > + lr_reg |= GICH_V2_LR_MAINTENANCE_IRQ; > + } > + else if ( p->desc != NULL ) > + { > + lr_reg |= GICH_V2_LR_HW | ((p->desc->irq & GICH_V2_LR_PHYSICAL_MASK ) > + << GICH_V2_LR_PHYSICAL_SHIFT); > } > > writel_gich(lr_reg, GICH_LR + lr * 4); Actually in case p->desc == NULL (the irq is not an hardware irq, it could be the virtual timer irq or the evtchn irq), you shouldn't need the maintenance interrupt, if the bug was really due to GICH_LR_HW not working correctly on OMAP5. This changes might only be better at "hiding" the real issue. Maybe the problem is exactly the opposite: the new scheme for avoiding maintenance interrupts doesn't work for software interrupts. The commit that should make them work correctly after the no-maintenance-irq commit is 394b7e587b05d0f4a5fd6f067b38339ab5a77121 If you look at the changes to gic_update_one_lr in that commit, you'll see that is going to set a software irq as PENDING if it is already ACTIVE. Maybe that doesn't work correctly on OMAP5. Could you try this patch on top of 394b7e587b05d0f4a5fd6f067b38339ab5a77121? It should help us understand if the problem is specifically with software irqs. diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index b7516c0..d8a17c9 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -66,7 +66,7 @@ static DEFINE_PER_CPU(u8, gic_cpu_id); /* Maximum cpu interface per GIC */ #define NR_GIC_CPU_IF 8 -#undef GIC_DEBUG +#define GIC_DEBUG 1 static void gic_update_one_lr(struct vcpu *v, int i); @@ -563,6 +563,8 @@ static inline void gic_set_lr(int lr, struct pending_irq *p, ((p->irq & GICH_LR_VIRTUAL_MASK) << GICH_LR_VIRTUAL_SHIFT); if ( p->desc != NULL ) lr_val |= GICH_LR_HW | (p->desc->irq << GICH_LR_PHYSICAL_SHIFT); + else + lr_val |= GICH_LR_MAINTENANCE_IRQ; GICH[GICH_LR + lr] = lr_val;