From patchwork Fri Nov 9 13:47:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 150640 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp189357ljp; Fri, 9 Nov 2018 05:47:36 -0800 (PST) X-Google-Smtp-Source: AJdET5dJs1grLZMrZ3upIKbmo/GhLfjU314zkO6P3jcj9nRgBMKi/ZylTUV0Wf3Dz/WPgQGYH/5U X-Received: by 2002:adf:a386:: with SMTP id l6-v6mr8561021wrb.110.1541771256522; Fri, 09 Nov 2018 05:47:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541771256; cv=none; d=google.com; s=arc-20160816; b=btzuuHxUjL5w4VUDDJVMVetZqMeewvlvF/fDKJlMDx0LYL9RA22e5LL6Ev0jywUzB4 k/de8z97K6UJhhDSbKKQI1Bq104cjIPhc7UK/4fC2qlQCCcXKpHsaYEAQaMjA1SHBn+h ELYxPC6ASGkfPUmjDmE3Fl64sGOSUuxB0ASCOWiVHEv0c1MXsRspwGNS5fOPaMOVhra0 nW4IFw8qkiVBLpQLN/nRcXnYvBUZg6M2Mki6qH1FWcE16oYxp7K+Bleg7s5FE3wb9hou NXgeIZpRAGBAlObppeTtDiqkUkOOf5cEoQgZUtvQ4QbETPx9/ufrPmN3nbOXKgtceDMc xnzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from; bh=iRP2duKp/W36udL721gPV0sBelTVzRafrOWXlaxczzY=; b=usbVoTdXBSD2/cqFL/m+oC2SRvmazw5Gdn1iQE/6EowWL3EZE8kInb0XdLUxLm+lZp 0yYieqjxbagk8ozRpAFARMJlsaQbZayYFU59Rl7XVZcj0Xero6YZsjKJi2Sao6ilw0Cq p+FJt7zVHiZbCkG8hkl0TKARUzl5w/nYA1SpPNwqiOSJgVxZbb3TgUfV1dK5UR9BRGQk l1IVz1hDzPnQRNbrUn/UP83L3Y03ozG1DI7oYH9tDFABzp5boObQ0yCIb2uBgmaSMUSt IU1FlJSm2MXv2nGkBwT/GkeTO7jJUQrs5J2GIQLPW8Qo9/kLgkHZ+WvIccioD0N8TidB 5UgQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id r67-v6si825285wma.3.2018.11.09.05.47.35 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 09 Nov 2018 05:47:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gL78I-0002kA-NU; Fri, 09 Nov 2018 13:47:34 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Adam Lackorzynski Subject: [PATCH for-v3.1 0/3] Fix handling of HCR.VI and VF Date: Fri, 9 Nov 2018 13:47:28 +0000 Message-Id: <20181109134731.11605-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 This patchset reverts commit 8a0fc3a29fc2315325400, which tried to implement HCR.VI and VF, and then reimplements it correctly. The implementation of HCR.VI and VF in that commit is not correct -- they do not track the overall "is there a pending VIRQ or VFIQ" status, but whether there is a pending interrupt due to "this mechanism", ie the hypervisor having set the VI/VF bits. The overall pending state for VIRQ and VFIQ is effectively the logical OR of the inbound lines from the GIC with the VI and VF bits. Commit 8a0fc3a29fc231 would result in pending VIRQ/VFIQ possibly being lost when the hypervisor wrote to HCR. Patch 1 reverts the broken implementation. Patch 2 adds tracking of the state of the input lines from the GIC (most of the complexity here is from having to handle inbound migration from older QEMU versions). Patch 3 implements HCR.{VI,VF} correctly. I plan to put the revert into rc1 at least, because it fixes a regression. thanks -- PMM Peter Maydell (3): Revert "target/arm: Implement HCR.VI and VF" target/arm: Track the state of our irq lines from the GIC explicitly target/arm: Correctly implement handling of HCR_EL2.{VI,VF} target/arm/cpu.h | 3 ++ target/arm/internals.h | 18 ++++++++++++ target/arm/cpu.c | 64 +++++++++++++++++++++++++++++++++++++++++- target/arm/helper.c | 57 +++++++++++-------------------------- target/arm/machine.c | 51 +++++++++++++++++++++++++++++++++ 5 files changed, 152 insertions(+), 41 deletions(-) -- 2.19.1