Message ID | 20181203203839.757-1-richard.henderson@linaro.org |
---|---|
Headers | show |
Series | target/arm: LOR, HPD, AA32HPD | expand |
On Mon, 3 Dec 2018 at 20:38, Richard Henderson <richard.henderson@linaro.org> wrote: > > Three relatively simple post-8.0 extensions. > > Changes since v1: > * Add TLOR access checks for LOR registers. > * Clean up access to HCR_EL2. > * Clean up setting of SCR_EL3. > * Other changes as noted within each patch. I've taken patches 1,2,3,4,7,9,10 into target-arm.next: > target/arm: Move id_aa64mmfr* to ARMISARegisters > target/arm: Add HCR_EL2 bits up to ARMv8.5 > target/arm: Add SCR_EL3 bits up to ARMv8.5 > target/arm: Fix HCR_EL2.TGE check in arm_phys_excp_target_el > target/arm: Tidy scr_write > target/arm: Implement the ARMv8.1-HPD extension > target/arm: Implement the ARMv8.2-AA32HPD extension leaving 5,6,8 as needing rework: > target/arm: Introduce arm_hcr_el2_eff > target/arm: Use arm_hcr_el2_eff more places > target/arm: Implement the ARMv8.1-LOR extension thanks -- PMM