[0/4] riscv: Add semihosting support [v10]

This series first adapts the existing ARM semihosting code to be
architecture-neutral, then adds RISC-V semihosting support using that.

Patch 1/4 moves the ARM semihosting support code to common directories and
adapts the build system to match.

Patch 2/4 changes the public API to this code to use
architecture-independent names and types.

Patch 3/4 changes the internals of this code to use architecture
neutral types where practical, and adds helper functions to abstract
away the architecture-specific details.

Patch 4/4 adds the RISC-V support, including modifying the breakpoint
handling code to recognize a semihosting sequence and adding RISC-V
specific implementations of the helper functions.

Patchew URL: https://patchew.org/QEMU/20201026212853.92880-1-keithp@keithp.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20201026212853.92880-1-keithp@keithp.com
Subject: [PATCH 0/4] riscv: Add semihosting support [v10]

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]         patchew/20201026212853.92880-1-keithp@keithp.com -> patchew/20201026212853.92880-1-keithp@keithp.com
Switched to a new branch 'test'
e13a1a6 riscv: Add semihosting support [v10]
3ecdba3 semihosting: Change internal common-semi interfaces to use CPUState *
ee6bc19 semihosting: Change common-semi API to be architecture-independent
5565c62 semihosting: Move ARM semihosting code to shared directories

=== OUTPUT BEGIN ===
1/4 Checking commit 5565c62ebb1a (semihosting: Move ARM semihosting code to shared directories)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#21: 
rename from target/arm/arm-semi.c

total: 0 errors, 1 warnings, 27 lines checked

Patch 1/4 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
2/4 Checking commit ee6bc19d36dd (semihosting: Change common-semi API to be architecture-independent)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#66: 
new file mode 100644

total: 0 errors, 1 warnings, 163 lines checked

Patch 2/4 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/4 Checking commit 3ecdba3733cf (semihosting: Change internal common-semi interfaces to use CPUState *)
ERROR: braces {} are necessary for all arms of this statement
#86: FILE: hw/semihosting/common-semi.c:142:
+    if (is_a64(env))
[...]
+    else
[...]

ERROR: braces {} are necessary for all arms of this statement
#97: FILE: hw/semihosting/common-semi.c:153:
+    if (is_a64(env))
[...]
+    else
[...]

WARNING: line over 80 characters
#205: FILE: hw/semihosting/common-semi.c:346:
+static void common_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err)

WARNING: line over 80 characters
#213: FILE: hw/semihosting/common-semi.c:351:
+    cpu_memory_rw_debug(cs, common_semi_flen_buf(cs) + 32, (uint8_t *)&size, 4, 0);

WARNING: line over 80 characters
#230: FILE: hw/semihosting/common-semi.c:360:
+static void common_semi_open_cb(CPUState *cs, target_ulong ret, target_ulong err)

WARNING: line over 80 characters
#257: FILE: hw/semihosting/common-semi.c:373:
+static target_ulong common_semi_gdb_syscall(CPUState *cs, gdb_syscall_complete_cb cb,

WARNING: line over 80 characters
#599: FILE: hw/semihosting/common-semi.c:765:
+            ret = common_semi_gdb_syscall(cs, common_semi_open_cb, "open,%s,%x,1a4", arg0,

WARNING: line over 80 characters
#600: FILE: hw/semihosting/common-semi.c:766:
+                                          (int)arg2+1, gdb_open_modeflags[arg1]);

ERROR: spaces required around that '+' (ctx:VxV)
#600: FILE: hw/semihosting/common-semi.c:766:
+                                          (int)arg2+1, gdb_open_modeflags[arg1]);
                                                    ^

ERROR: spaces required around that '+' (ctx:VxV)
#702: FILE: hw/semihosting/common-semi.c:863:
+                                          arg0, (int)arg1+1);
                                                          ^

WARNING: line over 80 characters
#722: FILE: hw/semihosting/common-semi.c:881:
+                                           arg0, (int)arg1+1, arg2, (int)arg3+1);

ERROR: spaces required around that '+' (ctx:VxV)
#722: FILE: hw/semihosting/common-semi.c:881:
+                                           arg0, (int)arg1+1, arg2, (int)arg3+1);
                                                           ^

ERROR: spaces required around that '+' (ctx:VxV)
#722: FILE: hw/semihosting/common-semi.c:881:
+                                           arg0, (int)arg1+1, arg2, (int)arg3+1);
                                                                              ^

ERROR: spaces required around that '+' (ctx:VxV)
#750: FILE: hw/semihosting/common-semi.c:907:
+                                           arg0, (int)arg1+1);
                                                           ^

total: 7 errors, 7 warnings, 767 lines checked

Patch 3/4 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

4/4 Checking commit e13a1a60ecc7 (riscv: Add semihosting support [v10])
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20201026212853.92880-1-keithp@keithp.com/testing.checkpatch/?type=message.
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