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[174.92.28.28]) by smtp.googlemail.com with ESMTPSA id a8sm2525707qtx.9.2021.03.31.19.41.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Mar 2021 19:41:54 -0700 (PDT) From: Shashi Mallela To: peter.maydell@linaro.org, leif@nuviainc.com, rad@semihalf.com Subject: [PATCH v2 0/8] GICv3 LPI and ITS feature implementation Date: Wed, 31 Mar 2021 22:41:44 -0400 Message-Id: <20210401024152.203896-1-shashi.mallela@linaro.org> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f35; envelope-from=shashi.mallela@linaro.org; helo=mail-qv1-xf35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This patchset implements qemu device model for enabling physical LPI support and ITS functionality in GIC as per GICv3 specification. Both flat table and 2 level tables are implemented.The ITS commands for adding/deleting ITS table entries,trigerring LPI interrupts are implemented.Translated LPI interrupt ids are processed by redistributor to determine priority and set pending state appropriately before forwarding the same to cpu interface. The ITS feature support has been added to sbsa-ref platform as well as virt platform,wherein the emulated functionality co-exists with kvm kernel functionality. Changes in v2: - used FIELD to avoid manual mask definition/manipulation - defined registers in patches that first use them - changed LOG_GUEST_ERROR to LOG_UNIMP for unimplemented code - all kvm-unit-tests passed except 1 inapplicable case of its-trigger which assumes presence of redistributor caching Shashi Mallela (8): hw/intc: GICv3 ITS initial framework hw/intc: GICv3 ITS register definitions added hw/intc: GICv3 ITS command queue framework hw/intc: GICv3 ITS Command processing hw/intc: GICv3 ITS Feature enablement hw/intc: GICv3 redistributor ITS processing hw/arm/sbsa-ref: add ITS support in SBSA GIC hw/arm/virt: add ITS support in virt GIC hw/arm/sbsa-ref.c | 26 +- hw/arm/virt.c | 10 +- hw/intc/arm_gicv3.c | 6 + hw/intc/arm_gicv3_common.c | 16 + hw/intc/arm_gicv3_cpuif.c | 15 +- hw/intc/arm_gicv3_dist.c | 22 +- hw/intc/arm_gicv3_its.c | 1359 ++++++++++++++++++++++++ hw/intc/arm_gicv3_its_common.c | 54 +- hw/intc/arm_gicv3_its_kvm.c | 2 +- hw/intc/arm_gicv3_redist.c | 152 ++- hw/intc/gicv3_internal.h | 177 ++- hw/intc/meson.build | 1 + include/hw/intc/arm_gicv3_common.h | 14 + include/hw/intc/arm_gicv3_its_common.h | 40 +- target/arm/kvm_arm.h | 4 +- 15 files changed, 1867 insertions(+), 31 deletions(-) create mode 100644 hw/intc/arm_gicv3_its.c -- 2.27.0