From patchwork Sat Oct 16 17:13:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515859 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp87895imp; Sat, 16 Oct 2021 10:16:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJydLuGIWAm/CbWepjig1Ds/wJ3m9yW610LDCqc74Ugs3Jrogvk8K8cl2yp9tPe1NIP4AQiK X-Received: by 2002:a1f:1f0a:: with SMTP id f10mr18676316vkf.21.1634404615334; Sat, 16 Oct 2021 10:16:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634404615; cv=none; d=google.com; s=arc-20160816; b=xVrzA3XzIFOJqTAylwOHviZXR9m594gzl9KxdsSENEzeN0SDu78E/+Pc703g2Vdwcv RtBXijdTXTssVQWjZHe/UzjQxGzIGJMgI2yNdStUcoywEA5+v4sCuEwJkc0jD5zM6zdG CM9PUOf5Fe7tg/tBAShadiQc9fBUE+ksdmi7DnYuElt4rPHDRYdUUOBgWQQYfPP7MIvc XvhYnCKcwRwU0aWuuXXstwg+0k/Wf4f3K+N41Ve7HmrlM98tiV2i+hywPwUyV5ksuuq+ qCTiJlwVgUM9JE3rqcvXI6ToobOncUt4okBUQvZoc54fXdafzyVFlWJgcbUCblBFVMoY Guyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:to:from:dkim-signature; bh=4gLwwRS+S3qLR7K1/Zsn+88po1Ea6GHguAJyPwg+2Xs=; b=sw8CQxaDAhsXG+XZgI09N7pYZ44fUs+KENHEMaUYhI1OunzPFL3VUh6+FByoWu72Eo wK0CBJTmWLjzwp3uuus+xEJbUcCXm16EF9uo+rgT0U96NGeeZ0zm3GfTKeO3pnTpklr0 YA17/np0hSkMo9qwWvgq6Q4Gyywf0vDr2xkx/d1D9yo9JqOAwmWMz284Bbj1Ekv9S6e8 OMrXg+EFPFTKphncthd3Szr7puDWNZPon2aJbdRf9Byke5IejmtlhBwwedz/L3DddAWj WrBp8A9QAUQmuc75MsbGvgNOdy1/xI9HNHvlVnG2rhgleX/5nz5BxjySu0xrhNpPCVK5 6E6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="R/aEOtvS"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c23si9024198uan.253.2021.10.16.10.16.55 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 16 Oct 2021 10:16:55 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="R/aEOtvS"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36266 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbnIk-0000zs-JR for patch@linaro.org; Sat, 16 Oct 2021 13:16:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60366) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbnGF-0000yp-Uh for qemu-devel@nongnu.org; Sat, 16 Oct 2021 13:14:21 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:42864) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbnGB-00066H-JX for qemu-devel@nongnu.org; Sat, 16 Oct 2021 13:14:19 -0400 Received: by mail-pg1-x532.google.com with SMTP id 66so11678884pgc.9 for ; Sat, 16 Oct 2021 10:14:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=4gLwwRS+S3qLR7K1/Zsn+88po1Ea6GHguAJyPwg+2Xs=; b=R/aEOtvSSqzsT7XAOQlQL2K8c73h3OdYAXGyYSQXNFNL75fEAKy/snUm1pwvkQAdQ/ fVMR/+5c1lQRWwYA+D1JFSeeVDWeoY1GlNf6aFeJWSuTU0M6lqS+go8E04jEX/TV49RP q59n3ub86kmib0GdRoAFPZPOo86uDgsQ1BjNX1PFoyn885dZKSs/9oLSt5vdNx3xLNcb xW+bkjPFsB03yWaosWTFSRFcfh26XXVSpyv4ciQOBN9rSrnMI5mcIQLpOFQke6l1DXbN 8EraGKh+xwMkqV23OfqYDgKIhN+rKjqVJxrHsRtSC/Vk0A6LcQIjlWoMjwPxa08LEV4V GwbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=4gLwwRS+S3qLR7K1/Zsn+88po1Ea6GHguAJyPwg+2Xs=; b=NSh7gveATmEEig2sonhhpYWGfDeBAl6YGvw9I4PnpvQob5QCF+zhQS1k4oi8tgSi+U qV37yZmUceaNSIwCkFLRe5w5Qhd5CIebyeW659NJemQ0Za6VYl8CscmxhRvyFRocC2EW dI1V5YRuyIWRN2h5qZhqqQMAfzcn8iRXmxB04CXO0Mj4NFgHNRa+RNX/mGPEKsusuYFy FtqybOxJuMIX7Z3pP7Qr3CsZ62UQPuLJ20zGM9o/Kf8TFAfGoYyW2BNsyQ5OyQHGT9Mc aWDhYxUv3/ytMRq3fL2hyKzPizbrAm/TTMSh0UF30STlfA6lTtzzXzbuqVhozpqXP5Qp JwXw== X-Gm-Message-State: AOAM531l10PrSahDtVyBCJclsIz4lJ4XReDdmnxLYdY81PV2LHx8bUmt kLhx5pJcCQiENvh5/wokP++byPhfFrs= X-Received: by 2002:a65:5385:: with SMTP id x5mr14758415pgq.140.1634404453693; Sat, 16 Oct 2021 10:14:13 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id l4sm2330281pfc.121.2021.10.16.10.14.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Oct 2021 10:14:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 00/14] target/riscv: Rationalize XLEN and operand length Date: Sat, 16 Oct 2021 10:13:58 -0700 Message-Id: <20211016171412.3163784-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, frank.chang@sifive.com, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, frederic.petrot@univ-grenoble-alpes.fr, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is a partial patch set attempting to set things in the right direction for both the UXL and RV128 patch sets. Notable addition for v3 is the treatment of [MS]STATUS.SD. Because this bit changes position depending on XLEN, it's better to split it out. But since it's read-only and computable from [MS]STATUS.{FS,XS}, it is even better to not store it at all. I noticed this while reading Frank's RVV patches which add VS to be included in SD. r~ Changes for v3: * Fix CONFIG_ typo. * Fix ctzw typo. * Mark get_xlen unused (clang werror) * Compute MSTATUS_SD on demand. Changes for v2: * Set mxl/sxl/uxl at reset. * Set sxl/uxl in write_mstatus. Richard Henderson (14): target/riscv: Move cpu_get_tb_cpu_state out of line target/riscv: Create RISCVMXL enumeration target/riscv: Split misa.mxl and misa.ext target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl target/riscv: Add MXL/SXL/UXL to TB_FLAGS target/riscv: Use REQUIRE_64BIT in amo_check64 target/riscv: Properly check SEW in amo_op target/riscv: Replace is_32bit with get_xl/get_xlen target/riscv: Replace DisasContext.w with DisasContext.ol target/riscv: Use gen_arith_per_ol for RVM target/riscv: Adjust trans_rev8_32 for riscv64 target/riscv: Use gen_unary_per_ol for RVB target/riscv: Use gen_shift*_per_ol for RVB, RVI target/riscv: Compute mstatus.sd on demand target/riscv/cpu.h | 73 +++------- target/riscv/cpu_bits.h | 8 +- hw/riscv/boot.c | 2 +- linux-user/elfload.c | 2 +- linux-user/riscv/cpu_loop.c | 2 +- semihosting/arm-compat-semi.c | 2 +- target/riscv/cpu.c | 108 +++++++++------ target/riscv/cpu_helper.c | 92 ++++++++++++- target/riscv/csr.c | 104 ++++++++------ target/riscv/gdbstub.c | 10 +- target/riscv/machine.c | 10 +- target/riscv/monitor.c | 4 +- target/riscv/translate.c | 174 ++++++++++++++++++------ target/riscv/insn_trans/trans_rvb.c.inc | 140 ++++++++++--------- target/riscv/insn_trans/trans_rvi.c.inc | 44 +++--- target/riscv/insn_trans/trans_rvm.c.inc | 36 +++-- target/riscv/insn_trans/trans_rvv.c.inc | 29 ++-- 17 files changed, 532 insertions(+), 308 deletions(-) -- 2.25.1