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([2607:fb90:5fe8:83ea:bbf4:c9ef:4f3:11c6]) by smtp.gmail.com with ESMTPSA id s36-20020a0568302aa400b0060603221259sm857273otu.41.2022.05.05.11.50.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 11:50:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v5 00/24] target/arm: Cleanups, new features, new cpus Date: Thu, 5 May 2022 13:49:42 -0500 Message-Id: <20220505185006.200555-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c36; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Changes for v4: * Rebase on master, where the second third is upstream. * Add ARM_CP_EL3_NO_EL2_C_NZ flag, and use that in the two cpregs called out by rule RJFFP that become constant but not zero. * Set SCTLR_EL1.TSCXT for user-only. Patches lacking review: 01-target-arm-Handle-cpreg-registration-for-missing-.patch 02-target-arm-Drop-EL3-no-EL2-fallbacks.patch 20-target-arm-Enable-FEAT_CSV2_2-for-cpu-max.patch r~ Richard Henderson (24): target/arm: Handle cpreg registration for missing EL target/arm: Drop EL3 no EL2 fallbacks target/arm: Merge zcr reginfo target/arm: Adjust definition of CONTEXTIDR_EL2 target/arm: Move cortex impdef sysregs to cpu_tcg.c target/arm: Update qemu-system-arm -cpu max to cortex-a57 target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max target/arm: Split out aa32_max_features target/arm: Annotate arm_max_initfn with FEAT identifiers target/arm: Use field names for manipulating EL2 and EL3 modes target/arm: Enable FEAT_Debugv8p2 for -cpu max target/arm: Enable FEAT_Debugv8p4 for -cpu max target/arm: Add minimal RAS registers target/arm: Enable SCR and HCR bits for RAS target/arm: Implement virtual SError exceptions target/arm: Implement ESB instruction target/arm: Enable FEAT_RAS for -cpu max target/arm: Enable FEAT_IESB for -cpu max target/arm: Enable FEAT_CSV2 for -cpu max target/arm: Enable FEAT_CSV2_2 for -cpu max target/arm: Enable FEAT_CSV3 for -cpu max target/arm: Enable FEAT_DGH for -cpu max target/arm: Define cortex-a76 target/arm: Define neoverse-n1 docs/system/arm/emulation.rst | 10 + docs/system/arm/virt.rst | 2 + target/arm/cpregs.h | 11 + target/arm/cpu.h | 23 ++ target/arm/helper.h | 1 + target/arm/internals.h | 16 + target/arm/syndrome.h | 5 + target/arm/a32.decode | 16 +- target/arm/t32.decode | 18 +- hw/arm/sbsa-ref.c | 2 + hw/arm/virt.c | 2 + target/arm/cpu.c | 66 +++- target/arm/cpu64.c | 353 +++++++++++--------- target/arm/cpu_tcg.c | 227 +++++++++---- target/arm/helper.c | 600 ++++++++++++++++++++-------------- target/arm/op_helper.c | 43 +++ target/arm/translate-a64.c | 18 + target/arm/translate.c | 23 ++ 18 files changed, 949 insertions(+), 487 deletions(-)