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([2605:ef80:80a9:5c0e:1ec2:d482:4986:8538]) by smtp.gmail.com with ESMTPSA id u15-20020a05620a0c4f00b006cf19068261sm10061132qki.116.2022.09.25.03.51.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Sep 2022 03:51:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 00/17] tcg: CPUTLBEntryFull and TARGET_TB_PCREL Date: Sun, 25 Sep 2022 10:51:07 +0000 Message-Id: <20220925105124.82033-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2b; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Smooshing these two patch sets back together for review bandwidth. I hope to make this the next tcg-next pull. There are three from the first half, tlbentryfull, which are new. These are following a hallway conversation with Peter about bits in MemTxAttrs that are not actually related to memory transactions, and infrastructure to address a to-do in an Arm patch set. There are a few patches from the second half, pcrel, that have not been reviewed. 07-target-sparc-Use-tlb_set_page_full.patch 08-accel-tcg-Move-byte_swap-from-MemTxAttrs-to-CPUTL.patch 09-accel-tcg-Add-force_aligned-to-CPUTLBEntryFull.patch 10-accel-tcg-Remove-PageDesc-code_bitmap.patch 13-accel-tcg-Do-not-align-tb-page_addr-0.patch 15-accel-tcg-Introduce-tb_pc-and-tb_pc_log.patch 16-accel-tcg-Introduce-TARGET_TB_PCREL.patch r~ Richard Henderson (17): accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull accel/tcg: Drop addr member from SavedIOTLB accel/tcg: Suppress auto-invalidate in probe_access_internal accel/tcg: Introduce probe_access_full accel/tcg: Introduce tlb_set_page_full include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA target/sparc: Use tlb_set_page_full accel/tcg: Move byte_swap from MemTxAttrs to CPUTLBEntryFull accel/tcg: Add force_aligned to CPUTLBEntryFull accel/tcg: Remove PageDesc code_bitmap accel/tcg: Use bool for page_find_alloc accel/tcg: Use DisasContextBase in plugin_gen_tb_start accel/tcg: Do not align tb->page_addr[0] include/hw/core: Create struct CPUJumpCache accel/tcg: Introduce tb_pc and tb_pc_log accel/tcg: Introduce TARGET_TB_PCREL accel/tcg: Split log_cpu_exec into inline and slow path include/exec/cpu-all.h | 6 +- include/exec/cpu-defs.h | 54 ++++-- include/exec/exec-all.h | 84 ++++++++- include/exec/memattrs.h | 2 - include/exec/plugin-gen.h | 7 +- include/hw/core/cpu.h | 10 +- accel/tcg/cpu-exec.c | 108 +++++++---- accel/tcg/cputlb.c | 228 ++++++++++++++---------- accel/tcg/plugin-gen.c | 22 +-- accel/tcg/translate-all.c | 168 ++++++----------- accel/tcg/translator.c | 2 +- target/arm/cpu.c | 4 +- target/arm/mte_helper.c | 14 +- target/arm/sve_helper.c | 4 +- target/arm/translate-a64.c | 2 +- target/avr/cpu.c | 2 +- target/hexagon/cpu.c | 2 +- target/hppa/cpu.c | 4 +- target/i386/tcg/tcg-cpu.c | 2 +- target/loongarch/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/tcg/exception.c | 2 +- target/mips/tcg/sysemu/special_helper.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 4 +- target/rx/cpu.c | 2 +- target/s390x/tcg/mem_helper.c | 4 - target/sh4/cpu.c | 4 +- target/sparc/cpu.c | 2 +- target/sparc/mmu_helper.c | 123 ++++++------- target/tricore/cpu.c | 2 +- tcg/tcg.c | 6 +- 32 files changed, 501 insertions(+), 381 deletions(-)