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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020adffe90000000b002b8fe58d6desm12245202wrr.62.2023.01.30.10.25.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:25:00 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 00/23] target/arm: Implement FEAT_FGT fine-grained traps Date: Mon, 30 Jan 2023 18:24:36 +0000 Message-Id: <20230130182459.3309057-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This series implements the FEAT_FGT fine-grained traps architectural feature. The bulk of this is new system registers HFGRTR_EL2, HFGWTR_EL2, HFGITR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, which have bits that enable trapping of system register and system instruction accesses on a fine-grained basis (typically one or a few sysregs at a time). Changes v1->v2: * patch 6 updated to use RTH's suggestion of doing the check inline rather than in a helper function * all other patches are already reviewed In theory we could implement this with our existing ARMCPRegInfo::accessfn machinery, but we would end up with many many very nearly identical access functions. Instead this series adds a new ARMCPRegInfo::fgt field, which specifies which bit in which FGT register should be checked; this is then tested by code in the access_check_cp_reg helper function. A few bits in HFGITR_EL2 allow trapping of instructions which aren't handled by the ARMCPRegInfo mechanism: ERET and SVC. These we just implement "by hand". FEAT_FGT also adds new MDCR_EL3.TDCC and MDCR_EL2.TDCC bits for trapping the Debug Comms Channel registers; these we implement with a standard accessfn. The first seven patches are various cleanups and bugfixes that I noticed while I was doing the FEAT_FGT work. In particular, we weren't getting the priority of HSTR_EL2 traps right -- these should take priority over UNDEF-at-EL traps but not over UNDEF-at-EL0 traps. The rest of the series is FEAT_FGT itself. thanks -- PMM Peter Maydell (23): target/arm: Name AT_S1E1RP and AT_S1E1WP cpregs correctly target/arm: Correct syndrome for ATS12NSO* at Secure EL1 target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3} target/arm: Move do_coproc_insn() syndrome calculation earlier target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1 target/arm: Disable HSTR_EL2 traps if EL2 is not enabled target/arm: Define the FEAT_FGT registers target/arm: Implement FGT trapping infrastructure target/arm: Mark up sysregs for HFGRTR bits 0..11 target/arm: Mark up sysregs for HFGRTR bits 12..23 target/arm: Mark up sysregs for HFGRTR bits 24..35 target/arm: Mark up sysregs for HFGRTR bits 36..63 target/arm: Mark up sysregs for HDFGRTR bits 0..11 target/arm: Mark up sysregs for HDFGRTR bits 12..63 target/arm: Mark up sysregs for HFGITR bits 0..11 target/arm: Mark up sysregs for HFGITR bits 12..17 target/arm: Mark up sysregs for HFGITR bits 18..47 target/arm: Mark up sysregs for HFGITR bits 48..63 target/arm: Implement the HFGITR_EL2.ERET trap target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps target/arm: Enable FEAT_FGT on '-cpu max' docs/system/arm/emulation.rst | 1 + target/arm/cpregs.h | 484 +++++++++++++++++++++++++++++++++- target/arm/cpu.h | 18 ++ target/arm/internals.h | 20 ++ target/arm/syndrome.h | 10 + target/arm/translate.h | 6 + hw/intc/arm_gicv3_cpuif.c | 2 + target/arm/cpu64.c | 1 + target/arm/debug_helper.c | 46 +++- target/arm/helper.c | 245 ++++++++++++++++- target/arm/op_helper.c | 58 +++- target/arm/translate-a64.c | 22 +- target/arm/translate.c | 125 +++++---- 13 files changed, 974 insertions(+), 64 deletions(-) Tested-by: Fuad Tabba