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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n12-20020a05600c294c00b003fee777fd84sm5298849wmd.41.2023.09.15.11.54.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Sep 2023 11:54:55 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Marcin Juszkiewicz , Leif Lindholm , Radoslaw Biernacki Subject: [PATCH 0/2] target/arm: Implement Neoverse-N2 Date: Fri, 15 Sep 2023 19:54:51 +0100 Message-Id: <20230915185453.1871167-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This patchset implements a model of the Neoverse-N2 CPU. Because it's very similar to the Cortex-A710 we don't need to implement any new features for it; but because it supports 48 bit physical addresses we can use it in the sbsa-ref board. Patch 1 fixes a few minor errors in the A710 definition that I spotted while I was cross-checking it against the N2 TRM to see what had changed. Patch 2 is the new CPU model. thanks -- PMM Peter Maydell (2): target/arm: Correct minor errors in Cortex-A710 definition target/arm: Implement Neoverse N2 CPU model docs/system/arm/virt.rst | 1 + hw/arm/sbsa-ref.c | 1 + hw/arm/virt.c | 1 + target/arm/tcg/cpu64.c | 114 ++++++++++++++++++++++++++++++++++++++- 4 files changed, 115 insertions(+), 2 deletions(-) Tested-by: Marcin Juszkiewicz