Message ID | 20241101161125.1901394-1-peter.maydell@linaro.org |
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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381c10b7f80sm5658313f8f.20.2024.11.01.09.11.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2024 09:11:26 -0700 (PDT) From: Peter Maydell <peter.maydell@linaro.org> To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>, Steven Lee <steven_lee@aspeedtech.com>, Troy Lee <leetroy@gmail.com>, Jamin Lin <jamin_lin@aspeedtech.com>, Andrew Jeffery <andrew@codeconstruct.com.au>, Joel Stanley <joel@jms.id.au> Subject: [PATCH 0/2] hw/arm/aspeed_ast27x0: minor IRQ number cleanup Date: Fri, 1 Nov 2024 16:11:23 +0000 Message-Id: <20241101161125.1901394-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org |
Series |
hw/arm/aspeed_ast27x0: minor IRQ number cleanup
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On 11/1/24 17:11, Peter Maydell wrote: > In the course of a conversation on IRC with somebody who was using > the ast27x0 code as a model for a new board, I noticed that the > code currently defines a local ARCH_GIC_MAINT_IRQ with a different > value from the constant of the same name that we define in the > include/hw/arm/bsa.h header. This patchset cleans that up and > also another minor awkwardness that I spotted in the process. > > thanks > -- PMM > > Peter Maydell (2): > hw/arm/aspeed_ast27x0: Use bsa.h for PPI definitions > hw/arm/aspeed_ast27x0: Avoid hardcoded '256' in IRQ calculation > > hw/arm/aspeed_ast27x0.c | 22 +++++++++++----------- > 1 file changed, 11 insertions(+), 11 deletions(-) > Applied to aspeed-next. Thanks, C.