[0/8] hw/arm: Explicit number of GIC external IRQs for Cortex A9/A15 MPCore

Message ID	20250130182441.40480-1-philmd@linaro.org
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org> To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>, Rob Herring <robh@kernel.org>, qemu-arm@nongnu.org, Peter Maydell <peter.maydell@linaro.org>, Alistair Francis <alistair@alistair23.me>, Igor Mitsyanko <i.mitsyanko@gmail.com>, =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= <philmd@linaro.org> Subject: [PATCH 0/8] hw/arm: Explicit number of GIC external IRQs for Cortex A9/A15 MPCore Date: Thu, 30 Jan 2025 19:24:33 +0100 Message-ID: <20250130182441.40480-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	hw/arm: Explicit number of GIC external IRQs for Cortex A9/A15 MPCore \| expand [0/8] hw/arm: Explicit number of GIC external IRQs for Cortex A9/A15 MPCore [1/8] hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL' definition [2/8] hw/arm/exynos4210: Explicit number of GIC external IRQs [3/8] hw/arm/realview: Explicit number of GIC external IRQs [4/8] hw/arm/xilinx_zynq: Replace IRQ_OFFSET -> GIC_INTERNAL [5/8] hw/arm/xilinx_zynq: Explicit number of GIC external IRQs [6/8] hw/arm/vexpress: Explicit number of GIC external IRQs [7/8] hw/arm/highbank: Explicit number of GIC external IRQs [8/8] hw/cpu/arm_mpcore: Remove default values for GIC external IRQs

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20250130182441.40480-1-philmd@linaro.org

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Subject: [PATCH 0/8] hw/arm: Explicit number of GIC external IRQs for Cortex
 A9/A15 MPCore
Date: Thu, 30 Jan 2025 19:24:33 +0100
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Series

hw/arm: Explicit number of GIC external IRQs for Cortex A9/A15 MPCore | expand

Message

Philippe Mathieu-Daudé Jan. 30, 2025, 6:24 p.m. UTC

Some boards based on Cortex-A9MP / Cortex-A15MP do not explicit
the number of external GIC IRQs, using some (implicit) default value,
not always trivial to figure out. Change that by removing the default
value, requiring MPCore objects to be created with the "num-irq" set.

Philippe Mathieu-Daudé (8):
  hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL'
    definition
  hw/arm/exynos4210: Explicit number of GIC external IRQs
  hw/arm/realview: Explicit number of GIC external IRQs
  hw/arm/xilinx_zynq: Replace IRQ_OFFSET -> GIC_INTERNAL
  hw/arm/xilinx_zynq: Explicit number of GIC external IRQs
  hw/arm/vexpress: Explicit number of GIC external IRQs
  hw/arm/highbank: Explicit number of GIC external IRQs
  hw/cpu/arm_mpcore: Remove default values for GIC external IRQs

 hw/arm/exynos4210.c  | 16 +++++++++++++--
 hw/arm/highbank.c    | 15 ++++++++++----
 hw/arm/realview.c    | 17 ++++++++++++++--
 hw/arm/vexpress.c    | 13 ++++++++++--
 hw/arm/xilinx_zynq.c | 47 +++++++++++++++++++++++++-------------------
 hw/cpu/a15mpcore.c   | 13 ++++++------
 hw/cpu/a9mpcore.c    | 14 ++++++-------
 7 files changed, 91 insertions(+), 44 deletions(-)