[v2,0/8] hw/arm: Explicit number of GIC external IRQs for Cortex A9/A15 MPCore

Message ID	20250212154333.28644-1-philmd@linaro.org
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org> To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>, Alistair Francis <alistair@alistair23.me>, Peter Maydell <peter.maydell@linaro.org>, Rob Herring <robh@kernel.org>, Igor Mitsyanko <i.mitsyanko@gmail.com>, qemu-arm@nongnu.org, =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org> Subject: [PATCH v2 0/8] hw/arm: Explicit number of GIC external IRQs for Cortex A9/A15 MPCore Date: Wed, 12 Feb 2025 16:43:25 +0100 Message-ID: <20250212154333.28644-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	hw/arm: Explicit number of GIC external IRQs for Cortex A9/A15 MPCore \| expand [v2,0/8] hw/arm: Explicit number of GIC external IRQs for Cortex A9/A15 MPCore [v2,1/8] hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL' definition [v2,2/8] hw/arm/exynos4210: Specify explicitly the GIC has 64 external IRQs [v2,3/8] hw/arm/realview: Specify explicitly the GIC has 64 external IRQs [v2,4/8] hw/arm/xilinx_zynq: Replace IRQ_OFFSET -> GIC_INTERNAL [v2,5/8] hw/arm/xilinx_zynq: Specify explicitly the GIC has 64 external IRQs [v2,6/8] hw/arm/vexpress: Specify explicitly the GIC has 64 external IRQs [v2,7/8] hw/arm/highbank: Specify explicitly the GIC has 128 external IRQs [v2,8/8] hw/cpu/arm_mpcore: Remove default values for GIC external IRQs

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20250212154333.28644-1-philmd@linaro.org

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Subject: [PATCH v2 0/8] hw/arm: Explicit number of GIC external IRQs for
 Cortex A9/A15 MPCore
Date: Wed, 12 Feb 2025 16:43:25 +0100
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Series

hw/arm: Explicit number of GIC external IRQs for Cortex A9/A15 MPCore | expand

Message

Philippe Mathieu-Daudé Feb. 12, 2025, 3:43 p.m. UTC

Some boards based on Cortex-A9MP / Cortex-A15MP do not explicit
the number of external GIC IRQs, using some (implicit) default value,
not always trivial to figure out. Change that by removing the default
value, requiring MPCore objects to be created with the "num-irq" set.

Since v1:
- Remove generic comments (Peter)

Philippe Mathieu-Daudé (8):
  hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL'
    definition
  hw/arm/exynos4210: Specify explicitly the GIC has 64 external IRQs
  hw/arm/realview: Specify explicitly the GIC has 64 external IRQs
  hw/arm/xilinx_zynq: Replace IRQ_OFFSET -> GIC_INTERNAL
  hw/arm/xilinx_zynq: Specify explicitly the GIC has 64 external IRQs
  hw/arm/vexpress: Specify explicitly the GIC has 64 external IRQs
  hw/arm/highbank: Specify explicitly the GIC has 128 external IRQs
  hw/cpu/arm_mpcore: Remove default values for GIC external IRQs

 hw/arm/exynos4210.c  | 10 ++++++++--
 hw/arm/highbank.c    |  8 ++++----
 hw/arm/realview.c    | 11 +++++++++--
 hw/arm/vexpress.c    |  7 +++++--
 hw/arm/xilinx_zynq.c | 43 ++++++++++++++++++++++---------------------
 hw/cpu/a15mpcore.c   | 18 ++++++++++++------
 hw/cpu/a9mpcore.c    | 18 ++++++++++++------
 7 files changed, 72 insertions(+), 43 deletions(-)