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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d8fcd78bdsm146514415e9.24.2025.04.01.01.09.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Apr 2025 01:09:40 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-10.1 00/24] cpus: Restrict SoftMMU mmu_index() to TCG Date: Tue, 1 Apr 2025 10:09:13 +0200 Message-ID: <20250401080938.32278-1-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org mmu_index() is specific to TCG SoftMMU, move CPUClass::mmu_index() to TCGCPUOps::mmu_index(). Philippe Mathieu-Daudé (24): hw/core/cpu: Update CPUClass::mmu_index docstring accel/tcg: Introduce TCGCPUOps::mmu_index() callback target/alpha: Restrict SoftMMU mmu_index() to TCG target/arm: Restrict SoftMMU mmu_index() to TCG target/avr: Restrict SoftMMU mmu_index() to TCG target/hppa: Restrict SoftMMU mmu_index() to TCG target/i386: Remove unused cpu_(ldub,stb)_kernel macros target/i386: Restrict cpu_mmu_index_kernel() to TCG target/i386: Restrict SoftMMU mmu_index() to TCG target/loongarch: Restrict SoftMMU mmu_index() to TCG target/m68k: Restrict SoftMMU mmu_index() to TCG target/microblaze: Restrict SoftMMU mmu_index() to TCG target/mips: Restrict SoftMMU mmu_index() to TCG target/openrisc: Restrict SoftMMU mmu_index() to TCG target/ppc: Restrict SoftMMU mmu_index() to TCG target/riscv: Restrict SoftMMU mmu_index() to TCG target/rx: Restrict SoftMMU mmu_index() to TCG target/s390x: Restrict SoftMMU mmu_index() to TCG target/sh4: Restrict SoftMMU mmu_index() to TCG target/sparc: Restrict SoftMMU mmu_index() to TCG target/tricore: Restrict SoftMMU mmu_index() to TCG target/xtensa: Restrict SoftMMU mmu_index() to TCG hw/core/cpu: Remove CPUClass::mmu_index() exec: Restrict cpu-mmu-index.h to accel/tcg/ include/{exec => accel/tcg}/cpu-mmu-index.h | 9 +++--- include/accel/tcg/cpu-ops.h | 3 ++ include/exec/cpu_ldst.h | 2 +- include/hw/core/cpu.h | 3 -- target/i386/cpu.h | 3 -- target/i386/tcg/seg_helper.h | 10 +++--- target/i386/tcg/tcg-cpu.h | 2 ++ accel/tcg/translator.c | 2 +- semihosting/uaccess.c | 2 +- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 13 ++++---- target/arm/gdbstub64.c | 2 +- target/avr/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/hppa/mem_helper.c | 2 +- target/i386/cpu.c | 34 --------------------- target/i386/tcg/seg_helper.c | 17 +++++++++++ target/i386/tcg/tcg-cpu.c | 18 +++++++++++ target/i386/tcg/translate.c | 2 +- target/loongarch/cpu.c | 2 +- target/loongarch/cpu_helper.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/microblaze/helper.c | 2 +- target/microblaze/mmu.c | 2 +- target/mips/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/openrisc/translate.c | 2 +- target/ppc/cpu_init.c | 2 +- target/riscv/cpu.c | 6 ---- target/riscv/tcg/tcg-cpu.c | 6 ++++ target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 4 +-- target/sparc/mmu_helper.c | 2 +- target/tricore/cpu.c | 2 +- target/tricore/helper.c | 2 +- target/xtensa/cpu.c | 2 +- target/xtensa/mmu_helper.c | 2 +- 40 files changed, 91 insertions(+), 91 deletions(-) rename include/{exec => accel/tcg}/cpu-mmu-index.h (78%) Reviewed-by: Richard Henderson