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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73e25912fb9sm8469976b3a.34.2025.04.28.13.10.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 13:10:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH 00/10] accel/tcg: Compile cpu-exec.c twice Date: Mon, 28 Apr 2025 13:10:18 -0700 Message-ID: <20250428201028.1699157-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org More work toward single-binary. r~ Richard Henderson (10): accel/tcg: Generalize fake_user_interrupt test accel/tcg: Unconditionally use CPU_DUMP_CCOP in log_cpu_exec accel/tcg: Introduce TCGCPUOps.cpu_exec_reset target/i386: Split out x86_cpu_exec_reset accel/tcg: Hoist cpu_get_tb_cpu_state decl to accl/tcg/cpu-ops.h target/riscv: Move cpu_get_tb_cpu_state to tcg-cpu.c accel/tcg: Return TCGTBCPUState from cpu_get_tb_cpu_state accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps accel/tcg: Split out accel/tcg/helper-retaddr.h accel/tcg: Compile cpu-exec.c twice accel/tcg/internal-common.h | 6 ++ include/accel/tcg/cpu-ldst.h | 34 ---------- include/accel/tcg/cpu-ops.h | 14 ++++ include/accel/tcg/helper-retaddr.h | 43 ++++++++++++ include/qemu/typedefs.h | 1 + target/alpha/cpu.h | 11 --- target/arm/cpu.h | 3 - target/arm/internals.h | 1 + target/avr/cpu.h | 18 ----- target/hexagon/cpu.h | 15 ----- target/hppa/cpu.h | 3 - target/i386/cpu.h | 14 ---- target/loongarch/cpu.h | 12 ---- target/m68k/cpu.h | 16 ----- target/microblaze/cpu.h | 8 --- target/mips/cpu.h | 9 --- target/openrisc/cpu.h | 10 --- target/ppc/cpu.h | 13 ---- target/ppc/internal.h | 2 + target/riscv/cpu.h | 3 - target/rx/cpu.h | 9 --- target/s390x/cpu.h | 9 --- target/sh4/cpu.h | 15 ----- target/sparc/cpu.h | 3 - target/tricore/cpu.h | 12 ---- target/xtensa/cpu.h | 68 ------------------- accel/tcg/cpu-exec.c | 103 +++++++++++------------------ accel/tcg/translate-all.c | 8 +-- accel/tcg/user-exec.c | 1 + target/alpha/cpu.c | 17 ++++- target/arm/cpu.c | 2 + target/arm/helper.c | 17 +++-- target/arm/tcg/cpu-v7m.c | 2 + target/arm/tcg/helper-a64.c | 1 + target/arm/tcg/sme_helper.c | 1 + target/arm/tcg/sve_helper.c | 1 + target/avr/cpu.c | 20 +++++- target/hexagon/cpu.c | 20 +++++- target/hppa/cpu.c | 15 +++-- target/i386/tcg/tcg-cpu.c | 33 ++++++++- target/loongarch/cpu.c | 19 +++++- target/m68k/cpu.c | 23 ++++++- target/microblaze/cpu.c | 16 ++++- target/mips/cpu.c | 13 ++++ target/openrisc/cpu.c | 17 ++++- target/ppc/cpu_init.c | 3 +- target/ppc/helper_regs.c | 19 +++--- target/ppc/mem_helper.c | 1 + target/riscv/cpu_helper.c | 97 --------------------------- target/riscv/tcg/tcg-cpu.c | 100 ++++++++++++++++++++++++++++ target/rx/cpu.c | 16 ++++- target/s390x/cpu.c | 17 +++-- target/s390x/tcg/mem_helper.c | 1 + target/sh4/cpu.c | 28 +++++++- target/sparc/cpu.c | 19 ++++-- target/tricore/cpu.c | 15 ++++- target/xtensa/cpu.c | 75 ++++++++++++++++++++- accel/tcg/meson.build | 2 +- 58 files changed, 561 insertions(+), 513 deletions(-) create mode 100644 include/accel/tcg/helper-retaddr.h