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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4535ead2449sm28200915e9.30.2025.06.19.06.13.21 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 19 Jun 2025 06:13:22 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Cameron Esfahani , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Julian Armistead , Radoslaw Biernacki , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Phil Dennis-Jordan , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Daniel_P?= =?utf-8?q?=2E_Berrang=C3=A9?= , Paolo Bonzini , Peter Maydell , Leif Lindholm , Pierrick Bouvier , Richard Henderson , qemu-arm@nongnu.org, Roman Bolshakov , Alexander Graf Subject: [PATCH 00/20] arm: Fixes and preparatory cleanups for split-accel Date: Thu, 19 Jun 2025 15:12:59 +0200 Message-ID: <20250619131319.47301-1-philmd@linaro.org> X-Mailer: git-send-email 2.49.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Omnibus series of ARM-related patches (noticed during the "split accel" PoC work). - Usual prototypes cleanups - Check TCG for EL2/EL3 features (and not !KVM or !HVF) - Improve HVF debugging - Correct HVF 'dtb_compatible' value for Linux - Fix HVF GTimer frequency (My M1 hardware has 24 MHz) (this implies accel/ rework w.r.t. QDev vCPU REALIZE) Regards, Phil. Philippe Mathieu-Daudé (20): target/arm: Remove arm_handle_psci_call() stub target/arm: Reduce arm_cpu_post_init() declaration scope target/arm: Unify gen_exception_internal() target/arm/hvf: Simplify GIC hvf_arch_init_vcpu() target/arm/hvf: Directly re-lock BQL after hv_vcpu_run() target/arm/hvf: Trace hv_vcpu_run() failures accel/hvf: Trace VM memory mapping target/arm/hvf: Log $pc in hvf_unknown_hvc() trace event target/arm/hvf: Correct dtb_compatible value target/arm: Restrict system register properties to system binary target/arm: Create GTimers *after* features finalized / accel realized accel: Keep reference to AccelOpsClass in AccelClass accel: Introduce AccelOpsClass::cpu_target_realize() hook accel/hvf: Add hvf_arch_cpu_realize() stubs target/arm/hvf: Really set Generic Timer counter frequency hw/arm/virt: Only require TCG || QTest to use TrustZone hw/arm/virt: Only require TCG || QTest to use virtualization extension hw/arm/virt: Rename cpu_post_init() -> post_cpus_gic_realized() hw/arm/sbsa-ref: Tidy up use of RAMLIMIT_GB definition tests/functional/sbsa-ref: Move where machine type is set meson.build | 1 + accel/hvf/trace.h | 2 + include/qemu/accel.h | 3 + include/system/accel-ops.h | 4 +- include/system/hvf.h | 3 + target/arm/cpu.h | 2 - target/arm/internals.h | 6 +- target/arm/tcg/translate.h | 1 + accel/accel-common.c | 4 ++ accel/accel-system.c | 3 +- accel/hvf/hvf-accel-ops.c | 8 +++ accel/tcg/tcg-accel-ops.c | 4 +- hw/arm/sbsa-ref.c | 8 ++- hw/arm/virt.c | 9 +-- target/arm/cpu.c | 71 ++++++++++++------------ target/arm/hvf/hvf.c | 46 +++++++++++---- target/arm/tcg/translate-a64.c | 6 -- target/arm/tcg/translate.c | 2 +- target/i386/hvf/hvf.c | 5 ++ accel/hvf/trace-events | 7 +++ target/arm/hvf/trace-events | 3 +- tests/functional/test_aarch64_sbsaref.py | 2 +- 22 files changed, 129 insertions(+), 71 deletions(-) create mode 100644 accel/hvf/trace.h create mode 100644 accel/hvf/trace-events