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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a6d117c66esm9121303f8f.47.2025.06.23.05.18.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 23 Jun 2025 05:18:47 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Leif Lindholm , qemu-arm@nongnu.org, =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Roman Bolshakov , Paolo Bonzini , Alexander Graf , Bernhard Beschow , John Snow , Thomas Huth , =?utf-8?q?Mar?= =?utf-8?q?c-Andr=C3=A9_Lureau?= , kvm@vger.kernel.org, Eric Auger , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Cameron Esfahani , Cleber Rosa , Radoslaw Biernacki , Phil Dennis-Jordan , Richard Henderson , =?utf-8?q?Alex_Benn=C3=A9?= =?utf-8?q?e?= Subject: [PATCH v3 00/26] arm: Fixes and preparatory cleanups for split-accel Date: Mon, 23 Jun 2025 14:18:19 +0200 Message-ID: <20250623121845.7214-1-philmd@linaro.org> X-Mailer: git-send-email 2.49.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Only the last patch is missing review (#26) Since v2: - Addressed thuth review comments Since v1: - Addressed rth's review comments Omnibus series of ARM-related patches (noticed during the "split accel" PoC work). - Usual prototypes cleanups - Check TCG for EL2/EL3 features (and not !KVM or !HVF) - Improve HVF debugging - Correct HVF 'dtb_compatible' value for Linux - Fix HVF GTimer frequency (My M1 hardware has 24 MHz) (this implies accel/ rework w.r.t. QDev vCPU REALIZE) - Expand functional tests w.r.t. HVF Regards, Phil. Philippe Mathieu-Daudé (26): target/arm: Remove arm_handle_psci_call() stub target/arm: Reduce arm_cpu_post_init() declaration scope target/arm: Unify gen_exception_internal() target/arm/hvf: Simplify GIC hvf_arch_init_vcpu() target/arm/hvf: Directly re-lock BQL after hv_vcpu_run() target/arm/hvf: Trace hv_vcpu_run() failures accel/hvf: Trace VM memory mapping target/arm/hvf: Log $pc in hvf_unknown_hvc() trace event target/arm: Correct KVM & HVF dtb_compatible value accel/hvf: Model PhysTimer register target/arm/hvf: Pass @target_el argument to hvf_raise_exception() target/arm: Restrict system register properties to system binary target/arm: Create GTimers *after* features finalized / accel realized accel: Keep reference to AccelOpsClass in AccelClass accel: Introduce AccelOpsClass::cpu_target_realize() hook accel/hvf: Add hvf_arch_cpu_realize() stubs target/arm/hvf: Really set Generic Timer counter frequency hw/arm/virt: Only require TCG || QTest to use TrustZone hw/arm/virt: Only require TCG || QTest to use virtualization extension hw/arm/virt: Rename cpu_post_init() -> post_cpus_gic_realized() hw/arm/sbsa-ref: Tidy up use of RAMLIMIT_GB definition tests/functional: Set sbsa-ref machine type in each test function tests/functional: Restrict nested Aarch64 Xen test to TCG tests/functional: Require TCG to run Aarch64 imx8mp-evk test tests/functional: Add hvf_available() helper tests/functional: Expand Aarch64 SMMU tests to run on HVF accelerator meson.build | 1 + accel/hvf/trace.h | 2 + include/qemu/accel.h | 3 + include/system/accel-ops.h | 4 +- include/system/hvf.h | 3 + target/arm/cpu.h | 2 - target/arm/internals.h | 6 +- target/arm/tcg/translate.h | 1 + accel/accel-common.c | 4 + accel/accel-system.c | 3 +- accel/hvf/hvf-accel-ops.c | 8 ++ accel/tcg/tcg-accel-ops.c | 4 +- hw/arm/sbsa-ref.c | 8 +- hw/arm/virt.c | 9 +- target/arm/cpu.c | 78 +++++++++-------- target/arm/hvf/hvf.c | 86 ++++++++++++------- target/arm/kvm.c | 2 +- target/arm/tcg/translate-a64.c | 6 -- target/arm/tcg/translate.c | 2 +- target/i386/hvf/hvf.c | 5 ++ accel/hvf/trace-events | 7 ++ python/qemu/utils/__init__.py | 2 +- python/qemu/utils/accel.py | 8 ++ target/arm/hvf/trace-events | 5 +- tests/functional/qemu_test/testcase.py | 6 +- tests/functional/test_aarch64_imx8mp_evk.py | 1 + tests/functional/test_aarch64_sbsaref.py | 5 +- .../functional/test_aarch64_sbsaref_alpine.py | 3 +- .../test_aarch64_sbsaref_freebsd.py | 3 +- tests/functional/test_aarch64_smmu.py | 12 ++- tests/functional/test_aarch64_xen.py | 1 + 31 files changed, 186 insertions(+), 104 deletions(-) create mode 100644 accel/hvf/trace.h create mode 100644 accel/hvf/trace-events