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Show patches with
: Series =
target/riscv: MSTATUS_SUM + cleanups
| 25 patches
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Delegate
------
Nobody
andy.doan@linaro.org
andy.doan@linaro.org
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Patch
Series
S/W/F
Date
Submitter
Delegate
State
[v7,25/25] target/riscv: Reorg sum check in get_physical_address
target/riscv: MSTATUS_SUM + cleanups
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2023-04-12
Richard Henderson
Accepted
[v7,24/25] target/riscv: Reorg access check in get_physical_address
target/riscv: MSTATUS_SUM + cleanups
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2023-04-12
Richard Henderson
Accepted
[v7,23/25] target/riscv: Merge checks for reserved pte flags
target/riscv: MSTATUS_SUM + cleanups
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2023-04-12
Richard Henderson
Accepted
[v7,22/25] target/riscv: Don't modify SUM with is_debug
target/riscv: MSTATUS_SUM + cleanups
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2023-04-12
Richard Henderson
Accepted
[v7,21/25] target/riscv: Suppress pte update with is_debug
target/riscv: MSTATUS_SUM + cleanups
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2023-04-12
Richard Henderson
Accepted
[v7,20/25] target/riscv: Move leaf pte processing out of level loop
target/riscv: MSTATUS_SUM + cleanups
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2023-04-12
Richard Henderson
New
[v7,19/25] target/riscv: Hoist pbmte and hade out of the level loop
target/riscv: MSTATUS_SUM + cleanups
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2023-04-12
Richard Henderson
Accepted
[v7,18/25] target/riscv: Hoist second stage mode change to callers
target/riscv: MSTATUS_SUM + cleanups
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2023-04-12
Richard Henderson
Accepted
[v7,17/25] target/riscv: Check SUM in the correct register
target/riscv: MSTATUS_SUM + cleanups
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2023-04-12
Richard Henderson
Accepted
[v7,16/25] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index
target/riscv: MSTATUS_SUM + cleanups
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-
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2023-04-12
Richard Henderson
Accepted
[v7,15/25] target/riscv: Move hstatus.spvp check to check_access_hlsv
target/riscv: MSTATUS_SUM + cleanups
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2023-04-12
Richard Henderson
Accepted
[v7,14/25] target/riscv: Introduce mmuidx_2stage
target/riscv: MSTATUS_SUM + cleanups
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-
2023-04-12
Richard Henderson
New
[v7,13/25] target/riscv: Introduce mmuidx_priv
target/riscv: MSTATUS_SUM + cleanups
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-
2023-04-12
Richard Henderson
New
[v7,12/25] target/riscv: Introduce mmuidx_sum
target/riscv: MSTATUS_SUM + cleanups
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-
2023-04-12
Richard Henderson
New
[v7,11/25] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT
target/riscv: MSTATUS_SUM + cleanups
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2023-04-12
Richard Henderson
New
[v7,10/25] target/riscv: Handle HLV, HSV via helpers
target/riscv: MSTATUS_SUM + cleanups
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2023-04-12
Richard Henderson
New
[v7,09/25] target/riscv: Use cpu_ld*_code_mmu for HLVX
target/riscv: MSTATUS_SUM + cleanups
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2023-04-12
Richard Henderson
Accepted
[v7,08/25] accel/tcg: Add cpu_ld*_code_mmu
target/riscv: MSTATUS_SUM + cleanups
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2023-04-12
Richard Henderson
Superseded
[v7,07/25] target/riscv: Reduce overhead of MSTATUS_SUM change
target/riscv: MSTATUS_SUM + cleanups
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2023-04-12
Richard Henderson
New
[v7,06/25] target/riscv: Separate priv from mmu_idx
target/riscv: MSTATUS_SUM + cleanups
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2023-04-12
Richard Henderson
New
[v7,05/25] target/riscv: Add a tb flags field for vstart
target/riscv: MSTATUS_SUM + cleanups
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2023-04-12
Richard Henderson
New
[v7,04/25] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags
target/riscv: MSTATUS_SUM + cleanups
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2023-04-12
Richard Henderson
Accepted
[v7,03/25] target/riscv: Encode the FS and VS on a normal way for tb flags
target/riscv: MSTATUS_SUM + cleanups
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2023-04-12
Richard Henderson
New
[v7,02/25] target/riscv: Add a general status enum for extensions
target/riscv: MSTATUS_SUM + cleanups
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2023-04-12
Richard Henderson
New
[v7,01/25] target/riscv: Extract virt enabled state from tb flags
target/riscv: MSTATUS_SUM + cleanups
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-
2023-04-12
Richard Henderson
New