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Show patches with
: Series =
[v3,01/16] target/riscv: cpu: Add a new 'resetvec' property
| State =
Action Required
| 3 patches
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andy.doan@linaro.org
andy.doan@linaro.org
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[v3,16/16] hw/riscv: sifive_u: Connect a DMA controller
[v3,01/16] target/riscv: cpu: Add a new 'resetvec' property
-
-
-
2020-09-01
Bin Meng
New
[v3,06/16] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs
[v3,01/16] target/riscv: cpu: Add a new 'resetvec' property
-
-
-
2020-09-01
Bin Meng
New
[v3,02/16] hw/riscv: hart: Add a new 'resetvec' property
[v3,01/16] target/riscv: cpu: Add a new 'resetvec' property
-
-
-
2020-09-01
Bin Meng
New