Show patches with: Series = target/riscv: Rationalize XLEN and operand length       |    State = Action Required       |    Archived = No       |   10 patches
Patch Series S/W/F Date Submitter Delegate State
[v6,14/15] target/riscv: Use riscv_csrrw_debug for cpu_dump target/riscv: Rationalize XLEN and operand length --- 2021-10-20 Richard Henderson New
[v6,13/15] target/riscv: Use gen_shift*_per_ol for RVB, RVI target/riscv: Rationalize XLEN and operand length --- 2021-10-20 Richard Henderson New
[v6,12/15] target/riscv: Use gen_unary_per_ol for RVB target/riscv: Rationalize XLEN and operand length --- 2021-10-20 Richard Henderson New
[v6,10/15] target/riscv: Use gen_arith_per_ol for RVM target/riscv: Rationalize XLEN and operand length --- 2021-10-20 Richard Henderson New
[v6,09/15] target/riscv: Replace DisasContext.w with DisasContext.ol target/riscv: Rationalize XLEN and operand length --- 2021-10-20 Richard Henderson New
[v6,08/15] target/riscv: Replace is_32bit with get_xl/get_xlen target/riscv: Rationalize XLEN and operand length --- 2021-10-20 Richard Henderson New
[v6,06/15] target/riscv: Use REQUIRE_64BIT in amo_check64 target/riscv: Rationalize XLEN and operand length --- 2021-10-20 Richard Henderson New
[v6,05/15] target/riscv: Add MXL/SXL/UXL to TB_FLAGS target/riscv: Rationalize XLEN and operand length --- 2021-10-20 Richard Henderson New
[v6,04/15] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl target/riscv: Rationalize XLEN and operand length --- 2021-10-20 Richard Henderson New
[v6,03/15] target/riscv: Split misa.mxl and misa.ext target/riscv: Rationalize XLEN and operand length --- 2021-10-20 Richard Henderson New