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Show patches with
: Series =
{tcg,aarch64}: Add TLB_CHECK_ALIGNED
| Archived =
No
| 9 patches
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andy.doan@linaro.org
andy.doan@linaro.org
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[v2,9/9] target/arm: Do memory type alignment check when translation enabled
{tcg,aarch64}: Add TLB_CHECK_ALIGNED
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2023-06-21
Richard Henderson
Superseded
[v2,8/9] target/arm: Do memory type alignment check when translation disabled
{tcg,aarch64}: Add TLB_CHECK_ALIGNED
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-
-
2023-06-21
Richard Henderson
Superseded
[v2,7/9] accel/tcg: Add TLB_CHECK_ALIGNED
{tcg,aarch64}: Add TLB_CHECK_ALIGNED
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-
-
2023-06-21
Richard Henderson
Superseded
[v2,6/9] accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull
{tcg,aarch64}: Add TLB_CHECK_ALIGNED
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2023-06-21
Richard Henderson
New
[v2,5/9] exec/memattrs: Remove target_tlb_bit*
{tcg,aarch64}: Add TLB_CHECK_ALIGNED
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-
-
2023-06-21
Richard Henderson
Superseded
[v2,4/9] target/arm: Support 32-byte alignment in pow2_align
{tcg,aarch64}: Add TLB_CHECK_ALIGNED
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-
-
2023-06-21
Richard Henderson
Superseded
[v2,3/9] accel/tcg: Renumber TLB_DISCARD_WRITE
{tcg,aarch64}: Add TLB_CHECK_ALIGNED
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-
-
2023-06-21
Richard Henderson
Superseded
[v2,2/9] accel/tcg: Move TLB_WATCHPOINT to TLB_SLOW_FLAGS_MASK
{tcg,aarch64}: Add TLB_CHECK_ALIGNED
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-
-
2023-06-21
Richard Henderson
Superseded
[v2,1/9] accel/tcg: Store some tlb flags in CPUTLBEntryFull
{tcg,aarch64}: Add TLB_CHECK_ALIGNED
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-
-
2023-06-21
Richard Henderson
Superseded