From patchwork Thu Feb 10 19:07:55 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 120 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:40:08 -0000 Delivered-To: patches@linaro.org Received: by 10.147.124.5 with SMTP id b5cs193492yan; Thu, 10 Feb 2011 11:07:58 -0800 (PST) Received: by 10.227.144.213 with SMTP id a21mr575062wbv.8.1297364877616; Thu, 10 Feb 2011 11:07:57 -0800 (PST) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk [81.2.115.146]) by mx.google.com with ESMTPS id g9si711060wbe.63.2011.02.10.11.07.56 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 10 Feb 2011 11:07:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.69) (envelope-from ) id 1Pnbrv-0003Ju-0W; Thu, 10 Feb 2011 19:07:55 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH] target-arm: Implement VMULL.P8 Date: Thu, 10 Feb 2011 19:07:55 +0000 Message-Id: <1297364875-12741-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.1 Implement VMULL.P8 (the 32x32->64 version of the polynomial multiply instruction). Signed-off-by: Peter Maydell --- target-arm/helpers.h | 1 + target-arm/neon_helper.c | 30 ++++++++++++++++++++++++++++++ target-arm/translate.c | 6 ++++-- 3 files changed, 35 insertions(+), 2 deletions(-) diff --git a/target-arm/helpers.h b/target-arm/helpers.h index 4d0de00..0d37abe 100644 --- a/target-arm/helpers.h +++ b/target-arm/helpers.h @@ -275,6 +275,7 @@ DEF_HELPER_2(neon_sub_u16, i32, i32, i32) DEF_HELPER_2(neon_mul_u8, i32, i32, i32) DEF_HELPER_2(neon_mul_u16, i32, i32, i32) DEF_HELPER_2(neon_mul_p8, i32, i32, i32) +DEF_HELPER_2(neon_mull_p8, i64, i32, i32) DEF_HELPER_2(neon_tst_u8, i32, i32, i32) DEF_HELPER_2(neon_tst_u16, i32, i32, i32) diff --git a/target-arm/neon_helper.c b/target-arm/neon_helper.c index 61890dd..b59ad38 100644 --- a/target-arm/neon_helper.c +++ b/target-arm/neon_helper.c @@ -895,6 +895,36 @@ uint32_t HELPER(neon_mul_p8)(uint32_t op1, uint32_t op2) return result; } +uint64_t HELPER(neon_mull_p8)(uint32_t op1, uint32_t op2) +{ + uint64_t result = 0; + uint64_t mask; + uint64_t op2ex = op2; + op2ex = (op2ex & 0xff) | + ((op2ex & 0xff00) << 8) | + ((op2ex & 0xff0000) << 16) | + ((op2ex & 0xff000000) << 24); + while (op1) { + mask = 0; + if (op1 & 1) { + mask |= 0xffff; + } + if (op1 & (1 << 8)) { + mask |= (0xffffU << 16); + } + if (op1 & (1 << 16)) { + mask |= (0xffffULL << 32); + } + if (op1 & (1 << 24)) { + mask |= (0xffffULL << 48); + } + result ^= op2ex & mask; + op1 = (op1 >> 1) & 0x7f7f7f7f; + op2ex <<= 1; + } + return result; +} + #define NEON_FN(dest, src1, src2) dest = (src1 & src2) ? -1 : 0 NEON_VOP(tst_u8, neon_u8, 4) NEON_VOP(tst_u16, neon_u16, 2) diff --git a/target-arm/translate.c b/target-arm/translate.c index 3087a5d..f640a50 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -5124,8 +5124,10 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) gen_neon_mull(cpu_V0, tmp, tmp2, size, u); break; case 14: /* Polynomial VMULL */ - cpu_abort(env, "Polynomial VMULL not implemented"); - + gen_helper_neon_mull_p8(cpu_V0, tmp, tmp2); + dead_tmp(tmp2); + dead_tmp(tmp); + break; default: /* 15 is RESERVED. */ return 1; }