From patchwork Mon Oct 10 16:24:06 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 4598 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 1A0CB23EF5 for ; Mon, 10 Oct 2011 16:24:15 +0000 (UTC) Received: from mail-yw0-f52.google.com (mail-yw0-f52.google.com [209.85.213.52]) by fiordland.canonical.com (Postfix) with ESMTP id DE651A181F4 for ; Mon, 10 Oct 2011 16:24:14 +0000 (UTC) Received: by mail-yw0-f52.google.com with SMTP id 31so8520098ywp.11 for ; Mon, 10 Oct 2011 09:24:14 -0700 (PDT) Received: by 10.223.92.144 with SMTP id r16mr33299221fam.23.1318263854408; Mon, 10 Oct 2011 09:24:14 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.24.41 with SMTP id r9cs122033laf; Mon, 10 Oct 2011 09:24:14 -0700 (PDT) Received: by 10.68.40.234 with SMTP id a10mr38119110pbl.120.1318263852626; Mon, 10 Oct 2011 09:24:12 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id b8si21017263pbd.30.2011.10.10.09.24.11 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 10 Oct 2011 09:24:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1RDIe8-0004Sc-68; Mon, 10 Oct 2011 17:24:08 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH v2 3/5] target-arm: Add ARM UDIV/SDIV support Date: Mon, 10 Oct 2011 17:24:06 +0100 Message-Id: <1318263848-17117-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1318263848-17117-1-git-send-email-peter.maydell@linaro.org> References: <1318263848-17117-1-git-send-email-peter.maydell@linaro.org> Add support for UDIV and SDIV in ARM mode. This is a new optional feature for A profile cores (Thumb mode has had UDIV and SDIV for M profile cores for some time). Signed-off-by: Peter Maydell --- target-arm/cpu.h | 1 + target-arm/helper.c | 5 ++++- target-arm/translate.c | 19 +++++++++++++++++++ 3 files changed, 24 insertions(+), 1 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 00e012e..af3904d 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -375,6 +375,7 @@ enum arm_features { ARM_FEATURE_V5, ARM_FEATURE_STRONGARM, ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ + ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ }; static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target-arm/helper.c b/target-arm/helper.c index 2cf6705..f70d979 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -207,7 +207,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) set_feature(env, ARM_FEATURE_VFP_FP16); set_feature(env, ARM_FEATURE_NEON); set_feature(env, ARM_FEATURE_THUMB2EE); - set_feature(env, ARM_FEATURE_THUMB_DIV); + set_feature(env, ARM_FEATURE_ARM_DIV); set_feature(env, ARM_FEATURE_V7MP); break; case ARM_CPUID_TI915T: @@ -261,6 +261,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) if (arm_feature(env, ARM_FEATURE_V7)) { set_feature(env, ARM_FEATURE_VAPA); } + if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { + set_feature(env, ARM_FEATURE_THUMB_DIV); + } } void cpu_reset(CPUARMState *env) diff --git a/target-arm/translate.c b/target-arm/translate.c index deb0bcf..812a9e7 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -7639,6 +7639,25 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) store_reg(s, rn, tmp); } break; + case 1: + case 3: + /* SDIV, UDIV */ + if (!arm_feature(env, ARM_FEATURE_ARM_DIV)) { + goto illegal_op; + } + if (((insn >> 5) & 7) || (rd != 15)) { + goto illegal_op; + } + tmp = load_reg(s, rm); + tmp2 = load_reg(s, rs); + if (insn & (1 << 21)) { + gen_helper_udiv(tmp, tmp, tmp2); + } else { + gen_helper_sdiv(tmp, tmp, tmp2); + } + tcg_temp_free_i32(tmp2); + store_reg(s, rn, tmp); + break; default: goto illegal_op; }