From patchwork Mon Dec 5 16:40:16 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 5463 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 9EE2B23E0C for ; Mon, 5 Dec 2011 16:40:29 +0000 (UTC) Received: from mail-lpp01m010-f52.google.com (mail-lpp01m010-f52.google.com [209.85.215.52]) by fiordland.canonical.com (Postfix) with ESMTP id 84296A18315 for ; Mon, 5 Dec 2011 16:40:29 +0000 (UTC) Received: by mail-lpp01m010-f52.google.com with SMTP id m6so354071lag.11 for ; Mon, 05 Dec 2011 08:40:29 -0800 (PST) Received: by 10.152.104.206 with SMTP id gg14mr6551099lab.41.1323103229427; Mon, 05 Dec 2011 08:40:29 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.41.198 with SMTP id h6cs266707lal; Mon, 5 Dec 2011 08:40:29 -0800 (PST) Received: by 10.52.68.240 with SMTP id z16mr5145508vdt.120.1323103226591; Mon, 05 Dec 2011 08:40:26 -0800 (PST) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id b20si7409350anj.152.2011.12.05.08.40.25 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 05 Dec 2011 08:40:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1RXbaW-0000Qv-QI; Mon, 05 Dec 2011 16:40:20 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Bill Carson Subject: [PATCH 3/7] hw/mpcore.c: Use the GIC memory regions for the CPU interface Date: Mon, 5 Dec 2011 16:40:16 +0000 Message-Id: <1323103220-1636-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1323103220-1636-1-git-send-email-peter.maydell@linaro.org> References: <1323103220-1636-1-git-send-email-peter.maydell@linaro.org> Switch to using the GIC memory regions for the CPU interface rather than hand implementing them as a subcase of mpcore_priv_read() and mpcore_priv_write(). Signed-off-by: Peter Maydell --- hw/mpcore.c | 35 ++++++++++------------------------- 1 files changed, 10 insertions(+), 25 deletions(-) diff --git a/hw/mpcore.c b/hw/mpcore.c index 3d64609..a0af1ad 100644 --- a/hw/mpcore.c +++ b/hw/mpcore.c @@ -41,7 +41,7 @@ static uint64_t mpcore_priv_read(void *opaque, target_phys_addr_t offset, { mpcore_priv_state *s = (mpcore_priv_state *)opaque; int id; - offset &= 0xfff; + offset &= 0xff; if (offset < 0x100) { /* SCU */ switch (offset) { @@ -57,17 +57,6 @@ static uint64_t mpcore_priv_read(void *opaque, target_phys_addr_t offset, default: goto bad_reg; } - } else if (offset < 0x600) { - /* Interrupt controller. */ - if (offset < 0x200) { - id = gic_get_current_cpu(); - } else { - id = (offset - 0x200) >> 8; - if (id >= s->num_cpu) { - return 0; - } - } - return gic_cpu_read(&s->gic, id, offset & 0xff); } bad_reg: hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset); @@ -78,8 +67,7 @@ static void mpcore_priv_write(void *opaque, target_phys_addr_t offset, uint64_t value, unsigned size) { mpcore_priv_state *s = (mpcore_priv_state *)opaque; - int id; - offset &= 0xfff; + offset &= 0xff; if (offset < 0x100) { /* SCU */ switch (offset) { @@ -92,16 +80,6 @@ static void mpcore_priv_write(void *opaque, target_phys_addr_t offset, default: goto bad_reg; } - } else if (offset < 0x600) { - /* Interrupt controller. */ - if (offset < 0x200) { - id = gic_get_current_cpu(); - } else { - id = (offset - 0x200) >> 8; - } - if (id < s->num_cpu) { - gic_cpu_write(&s->gic, id, offset & 0xff, value); - } } return; bad_reg: @@ -129,8 +107,15 @@ static void mpcore_priv_map_setup(mpcore_priv_state *s) SysBusDevice *busdev = sysbus_from_qdev(s->mptimer); memory_region_init(&s->container, "mpcode-priv-container", 0x2000); memory_region_init_io(&s->iomem, &mpcore_priv_ops, s, "mpcode-priv", - 0x1000); + 0x100); memory_region_add_subregion(&s->container, 0, &s->iomem); + /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs + * at 0x200, 0x300... + */ + for (i = 0; i < (s->num_cpu + 1); i++) { + target_phys_addr_t offset = 0x100 + (i * 0x100); + memory_region_add_subregion(&s->container, offset, &s->gic.cpuiomem[i]); + } /* Add the regions for timer and watchdog for "current CPU" and * for each specific CPU. */