From patchwork Fri Mar 30 13:00:39 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7543 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id AB75E23E29 for ; Fri, 30 Mar 2012 13:26:39 +0000 (UTC) Received: from mail-yw0-f52.google.com (mail-yw0-f52.google.com [209.85.213.52]) by fiordland.canonical.com (Postfix) with ESMTP id 7BF7EA1871D for ; Fri, 30 Mar 2012 13:26:39 +0000 (UTC) Received: by mail-yw0-f52.google.com with SMTP id p61so320221yhp.11 for ; Fri, 30 Mar 2012 06:26:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-forwarded-to:x-forwarded-for:delivered-to :received-spf:from:to:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=G7zjaATMU2xc5fCDV4HCQWoGv+DEhpiXA203hC5umII=; b=poLSmrchSRxgEfBrenWxEAefgoazTndRd+i6Oi3598yL+WJ17GgE1EWzfIp1nBe882 RNMi3fPsetiY9VI/RYZKN1w2ngF1LbE63Hi3TpogrUKfymYG7sITzJsJDGLPk0avzsNS LiHNdXjHXDy/cjhWsHPf0wy+b3Avstgh2DHJgbeYI6TDb6RC9GTftNrcN6/fqrsr07c0 OdFnL8dLojnmq3IJrHRK2NWF802CyUdv2QBzI9pLG5PsEz3R8bkgso+LTZnIbjBsJ8NZ Bdm2lKPZqxLWtiCgMJ+nDJiw8whvTtcz6zEd6OvJxt1IFY7a1UAF6KzWWX+gszDCDpp0 fTeg== MIME-Version: 1.0 Received: by 10.50.194.226 with SMTP id hz2mr1365685igc.44.1333113999087; Fri, 30 Mar 2012 06:26:39 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.5.205 with SMTP id 13csp22412ibw; Fri, 30 Mar 2012 06:26:37 -0700 (PDT) Received: by 10.14.204.3 with SMTP id g3mr546462eeo.75.1333113996401; Fri, 30 Mar 2012 06:26:36 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id e58si9934470wed.84.2012.03.30.06.26.35 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 30 Mar 2012 06:26:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SDbRb-00011S-SC for patches@linaro.org; Fri, 30 Mar 2012 14:00:43 +0100 From: Peter Maydell To: patches@linaro.org Subject: [PATCH 11/14] target-arm: Move cache ID register setup to cpu specific init fns Date: Fri, 30 Mar 2012 14:00:39 +0100 Message-Id: <1333112442-3871-12-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1333112442-3871-1-git-send-email-peter.maydell@linaro.org> References: <1333112442-3871-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQlonRZSE+5yyMME/xkRrn7mtIqL7mj344CvaSeBHox4LY9FITD5JDMrPBrbyFtmxkX7mVDm Move cache ID register reset out of cpu_reset_model_id() by creating a field for the reset value in ARMCPU and setting it up in the cpu specific init functions. Signed-off-by: Peter Maydell --- target-arm/cpu-qom.h | 2 ++ target-arm/cpu.c | 11 +++++++++++ target-arm/helper.c | 13 ++----------- 3 files changed, 15 insertions(+), 11 deletions(-) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index efdc0a8..55dc920 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -82,6 +82,8 @@ typedef struct ARMCPU { uint32_t id_isar3; uint32_t id_isar4; uint32_t id_isar5; + uint32_t clidr; + uint32_t ccsidr[16]; } ARMCPU; static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index a58bda2..c2eb998 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -280,6 +280,10 @@ static void cortex_a8_initfn(Object *obj) cpu->id_isar2 = 0x21232031; cpu->id_isar3 = 0x11112131; cpu->id_isar4 = 0x00111142; + cpu->clidr = (1 << 27) | (2 << 24) | 3; + cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ + cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ + cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ arm_cpu_postconfig_init(cpu); } @@ -314,6 +318,9 @@ static void cortex_a9_initfn(Object *obj) cpu->id_isar2 = 0x21232041; cpu->id_isar3 = 0x11112131; cpu->id_isar4 = 0x00111142; + cpu->clidr = (1 << 27) | (2 << 24) | 3; + cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */ + cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */ arm_cpu_postconfig_init(cpu); } @@ -346,6 +353,10 @@ static void cortex_a15_initfn(Object *obj) cpu->id_isar2 = 0x21232041; cpu->id_isar3 = 0x11112131; cpu->id_isar4 = 0x10011142; + cpu->clidr = 0x0a200023; + cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ + cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ + cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ arm_cpu_postconfig_init(cpu); } diff --git a/target-arm/helper.c b/target-arm/helper.c index a94f09f..5c4cfee 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -26,21 +26,10 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_ARM11MPCORE: break; case ARM_CPUID_CORTEXA8: - env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3; - env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */ - env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */ - env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */ break; case ARM_CPUID_CORTEXA9: - env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3; - env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */ - env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */ break; case ARM_CPUID_CORTEXA15: - env->cp15.c0_clid = 0x0a200023; - env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */ - env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */ - env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */ break; case ARM_CPUID_CORTEXM3: break; @@ -114,6 +103,8 @@ void cpu_state_reset(CPUARMState *env) env->cp15.c0_c2[4] = cpu->id_isar4; env->cp15.c0_c2[5] = cpu->id_isar5; env->cp15.c15_i_min = 0xff0; + env->cp15.c0_clid = cpu->clidr; + memcpy(env->cp15.c0_ccsid, cpu->ccsidr, ARRAY_SIZE(cpu->ccsidr)); if (arm_feature(env, ARM_FEATURE_IWMMXT)) { env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';