From patchwork Fri Mar 30 13:00:33 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7536 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 9B61123E42 for ; Fri, 30 Mar 2012 13:00:49 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 648EBA180FD for ; Fri, 30 Mar 2012 13:00:49 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so1328413iag.11 for ; Fri, 30 Mar 2012 06:00:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-forwarded-to:x-forwarded-for:delivered-to :received-spf:from:to:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=35iD35WliC3gtQ64Ufed4D6yJC5x8qCZ+5rR1NLGAy4=; b=aojFAVgjB11mmlSt17ivnspIjBkNNaHyolK4K9r9Sgba4nw53qbrFsjy24DFjdOOCW dJHzl/6dUSHNa56ndGbQXiAI1cT0rk4Yk9ImdW7lqh2+o4hnc81y8unD/NOnQHTTo87P owwsxM4ZVE2MRqLQa/n+snvY3+Av4SlDzJob29OFXWF4cApBU+kIrY+rja1NH88kCVIL s3X+7GBP5MNtefb8TEZWNWKX3sqTKex4GOSdfcJN8mO64T0YCZdbeTsf6kyto/m5Somz cHPkKiQB/AVDV0z4lfd7KdnG6y/nMBFkfE5ZTcwBO+PVnqH3VivOT//0rjKt9OGO4Ucr WUBA== MIME-Version: 1.0 Received: by 10.42.137.67 with SMTP id x3mr1100408ict.52.1333112449174; Fri, 30 Mar 2012 06:00:49 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.5.205 with SMTP id 13csp21187ibw; Fri, 30 Mar 2012 06:00:46 -0700 (PDT) Received: by 10.180.24.7 with SMTP id q7mr6259895wif.11.1333112445424; Fri, 30 Mar 2012 06:00:45 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id n3si2497562win.28.2012.03.30.06.00.44 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 30 Mar 2012 06:00:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SDbRb-000119-Dd for patches@linaro.org; Fri, 30 Mar 2012 14:00:43 +0100 From: Peter Maydell To: patches@linaro.org Subject: [PATCH 05/14] target-arm: Move CTR setup to per cpu init fns Date: Fri, 30 Mar 2012 14:00:33 +0100 Message-Id: <1333112442-3871-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1333112442-3871-1-git-send-email-peter.maydell@linaro.org> References: <1333112442-3871-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQnHviuCwwf4j0UCOiwl0pS7nSVUu+++2k6NtS64GMWNZTmlVqNs/nxXEThpnu11WXqvM+1H Move CTR (cache type register) value to an ARMCPU field set up by per-cpu init fns. Signed-off-by: Peter Maydell --- target-arm/cpu-qom.h | 1 + target-arm/cpu.c | 22 ++++++++++++++++++++++ target-arm/helper.c | 13 +------------ 3 files changed, 24 insertions(+), 12 deletions(-) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index e63ff76..fc147c4 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -66,6 +66,7 @@ typedef struct ARMCPU { uint32_t reset_fpsid; uint32_t mvfr0; uint32_t mvfr1; + uint32_t ctr; } ARMCPU; static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 444ba77..115561c 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -104,6 +104,7 @@ static void arm926_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP); cpu->midr = ARM_CPUID_ARM926; cpu->reset_fpsid = 0x41011090; + cpu->ctr = 0x1dd20d2; arm_cpu_postconfig_init(cpu); } @@ -113,6 +114,7 @@ static void arm946_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V5); set_feature(&cpu->env, ARM_FEATURE_MPU); cpu->midr = ARM_CPUID_ARM946; + cpu->ctr = 0x0f004006; arm_cpu_postconfig_init(cpu); } @@ -124,6 +126,7 @@ static void arm1026_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_AUXCR); cpu->midr = ARM_CPUID_ARM1026; cpu->reset_fpsid = 0x410110a0; + cpu->ctr = 0x1dd20d2; arm_cpu_postconfig_init(cpu); } @@ -136,6 +139,7 @@ static void arm1136_r2_initfn(Object *obj) cpu->reset_fpsid = 0x410120b4; cpu->mvfr0 = 0x11111111; cpu->mvfr1 = 0x00000000; + cpu->ctr = 0x1dd20d2; arm_cpu_postconfig_init(cpu); } @@ -149,6 +153,7 @@ static void arm1136_initfn(Object *obj) cpu->reset_fpsid = 0x410120b4; cpu->mvfr0 = 0x11111111; cpu->mvfr1 = 0x00000000; + cpu->ctr = 0x1dd20d2; arm_cpu_postconfig_init(cpu); } @@ -162,6 +167,7 @@ static void arm1176_initfn(Object *obj) cpu->reset_fpsid = 0x410120b5; cpu->mvfr0 = 0x11111111; cpu->mvfr1 = 0x00000000; + cpu->ctr = 0x1dd20d2; arm_cpu_postconfig_init(cpu); } @@ -175,6 +181,7 @@ static void arm11mpcore_initfn(Object *obj) cpu->reset_fpsid = 0x410120b4; cpu->mvfr0 = 0x11111111; cpu->mvfr1 = 0x00000000; + cpu->ctr = 0x1dd20d2; arm_cpu_postconfig_init(cpu); } @@ -198,6 +205,7 @@ static void cortex_a8_initfn(Object *obj) cpu->reset_fpsid = 0x410330c0; cpu->mvfr0 = 0x11110222; cpu->mvfr1 = 0x00011100; + cpu->ctr = 0x82048004; arm_cpu_postconfig_init(cpu); } @@ -218,6 +226,7 @@ static void cortex_a9_initfn(Object *obj) cpu->reset_fpsid = 0x41033090; cpu->mvfr0 = 0x11110222; cpu->mvfr1 = 0x01111111; + cpu->ctr = 0x80038003; arm_cpu_postconfig_init(cpu); } @@ -236,6 +245,7 @@ static void cortex_a15_initfn(Object *obj) cpu->reset_fpsid = 0x410430f0; cpu->mvfr0 = 0x10110222; cpu->mvfr1 = 0x11111111; + cpu->ctr = 0x8444c004; arm_cpu_postconfig_init(cpu); } @@ -245,6 +255,7 @@ static void ti925t_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V4T); set_feature(&cpu->env, ARM_FEATURE_OMAPCP); cpu->midr = ARM_CPUID_TI925T; + cpu->ctr = 0x5109149; arm_cpu_postconfig_init(cpu); } @@ -270,6 +281,7 @@ static void pxa250_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V5); set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->midr = ARM_CPUID_PXA250; + cpu->ctr = 0xd172172; arm_cpu_postconfig_init(cpu); } @@ -279,6 +291,7 @@ static void pxa255_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V5); set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->midr = ARM_CPUID_PXA255; + cpu->ctr = 0xd172172; arm_cpu_postconfig_init(cpu); } @@ -288,6 +301,7 @@ static void pxa260_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V5); set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->midr = ARM_CPUID_PXA260; + cpu->ctr = 0xd172172; arm_cpu_postconfig_init(cpu); } @@ -297,6 +311,7 @@ static void pxa261_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V5); set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->midr = ARM_CPUID_PXA261; + cpu->ctr = 0xd172172; arm_cpu_postconfig_init(cpu); } @@ -306,6 +321,7 @@ static void pxa262_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V5); set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->midr = ARM_CPUID_PXA262; + cpu->ctr = 0xd172172; arm_cpu_postconfig_init(cpu); } @@ -316,6 +332,7 @@ static void pxa270a0_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_XSCALE); set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->midr = ARM_CPUID_PXA270_A0; + cpu->ctr = 0xd172172; arm_cpu_postconfig_init(cpu); } @@ -326,6 +343,7 @@ static void pxa270a1_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_XSCALE); set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->midr = ARM_CPUID_PXA270_A1; + cpu->ctr = 0xd172172; arm_cpu_postconfig_init(cpu); } @@ -336,6 +354,7 @@ static void pxa270b0_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_XSCALE); set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->midr = ARM_CPUID_PXA270_B0; + cpu->ctr = 0xd172172; arm_cpu_postconfig_init(cpu); } @@ -346,6 +365,7 @@ static void pxa270b1_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_XSCALE); set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->midr = ARM_CPUID_PXA270_B1; + cpu->ctr = 0xd172172; arm_cpu_postconfig_init(cpu); } @@ -356,6 +376,7 @@ static void pxa270c0_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_XSCALE); set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->midr = ARM_CPUID_PXA270_C0; + cpu->ctr = 0xd172172; arm_cpu_postconfig_init(cpu); } @@ -370,6 +391,7 @@ static void pxa270c5_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); set_feature(&cpu->env, ARM_FEATURE_V7MP); cpu->midr = ARM_CPUID_PXA270_C5; + cpu->ctr = 0xd172172; arm_cpu_postconfig_init(cpu); } diff --git a/target-arm/helper.c b/target-arm/helper.c index aeffd6b..e1314c2 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -51,15 +51,12 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) { switch (id) { case ARM_CPUID_ARM926: - env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c1_sys = 0x00090078; break; case ARM_CPUID_ARM946: - env->cp15.c0_cachetype = 0x0f004006; env->cp15.c1_sys = 0x00000078; break; case ARM_CPUID_ARM1026: - env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c1_sys = 0x00090078; break; case ARM_CPUID_ARM1136: @@ -75,24 +72,20 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) */ memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t)); - env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM1176: memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t)); - env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM11MPCORE: memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t)); - env->cp15.c0_cachetype = 0x1dd20d2; break; case ARM_CPUID_CORTEXA8: memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t)); - env->cp15.c0_cachetype = 0x82048004; env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3; env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */ env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */ @@ -102,7 +95,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_CORTEXA9: memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t)); - env->cp15.c0_cachetype = 0x80038003; env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3; env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */ env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */ @@ -111,7 +103,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_CORTEXA15: memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, cortexa15_cp15_c0_c2, 8 * sizeof(uint32_t)); - env->cp15.c0_cachetype = 0x8444c004; env->cp15.c0_clid = 0x0a200023; env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */ env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */ @@ -124,7 +115,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) break; case ARM_CPUID_TI915T: case ARM_CPUID_TI925T: - env->cp15.c0_cachetype = 0x5109149; env->cp15.c1_sys = 0x00000070; env->cp15.c15_i_max = 0x000; env->cp15.c15_i_min = 0xff0; @@ -135,7 +125,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_PXA261: case ARM_CPUID_PXA262: /* JTAG_ID is ((id << 28) | 0x09265013) */ - env->cp15.c0_cachetype = 0xd172172; env->cp15.c1_sys = 0x00000078; break; case ARM_CPUID_PXA270_A0: @@ -146,7 +135,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_PXA270_C5: /* JTAG_ID is ((id << 28) | 0x09265013) */ env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; - env->cp15.c0_cachetype = 0xd172172; env->cp15.c1_sys = 0x00000078; break; case ARM_CPUID_SA1100: @@ -185,6 +173,7 @@ void cpu_state_reset(CPUARMState *env) env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; + env->cp15.c0_cachetype = cpu->ctr; #if defined (CONFIG_USER_ONLY) env->uncached_cpsr = ARM_CPU_MODE_USR;