From patchwork Sat Apr 14 16:42:20 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7832 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 153A023E23 for ; Sat, 14 Apr 2012 16:56:50 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id C990EA185C0 for ; Sat, 14 Apr 2012 16:56:49 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so7611950iag.11 for ; Sat, 14 Apr 2012 09:56:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=4yUYbwg0lQeXRkD5eoCd8Qtz+a+90/5z7SKJX5inJzo=; b=TA3kHdVUOs0mJQy1H8UnpITNRXhbW7AH4uKNKEAdEupr8jvFpdDUJ/370uz0HtkJlo Ss+hL+LZ2Ogy/J6FeLOCkZq18i1IbKN3sSq9mmCS3kTIFGuqlQlK32WmVr/v/FEEhqo5 ZVtRmu1hYYU1Cfpq/o6H1XMSY04CRA8ZR9JupvO/7URjgEIOG3VjPI/XsUgzC/M1ylnP DWFxgohLD1Fbo4O3cpqdZS0hTCehEm0tU0rDcALn8e8f2cR6Q3MD7KlcHpWLVm8vFvhB qQyBwHL5g4wjVHCcVbwNmSh3V+bSwQx/MtY34PwSS0XbrmDFaWvTABn7ytOEPjuHVZrN xLoA== Received: by 10.50.149.163 with SMTP id ub3mr1546605igb.30.1334422609607; Sat, 14 Apr 2012 09:56:49 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.70.69 with SMTP id c5csp90782ibj; Sat, 14 Apr 2012 09:56:49 -0700 (PDT) Received: by 10.180.92.130 with SMTP id cm2mr5311922wib.4.1334422608538; Sat, 14 Apr 2012 09:56:48 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id v49si13089155wec.119.2012.04.14.09.56.47 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 14 Apr 2012 09:56:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SJ63M-00087A-R2; Sat, 14 Apr 2012 17:42:24 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook , Anthony Liguori Subject: [PATCH v2 11/14] target-arm: Move cache ID register setup to cpu specific init fns Date: Sat, 14 Apr 2012 17:42:20 +0100 Message-Id: <1334421743-31146-13-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1334421743-31146-1-git-send-email-peter.maydell@linaro.org> References: <1334421743-31146-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQljBEBrS5ZILVoiGse/tEklGOCDN1IDsjH8WDMZkDfU/MRcgXVVtHssmdA90PgonU5v+HW5 Move cache ID register reset out of cpu_reset_model_id() by creating a field for the reset value in ARMCPU and setting it up in the cpu specific init functions. Signed-off-by: Peter Maydell Acked-by: Andreas Färber --- target-arm/cpu-qom.h | 5 +++++ target-arm/cpu.c | 11 +++++++++++ target-arm/helper.c | 13 ++----------- 3 files changed, 18 insertions(+), 11 deletions(-) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 7603eff..b6c044a 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -89,6 +89,11 @@ typedef struct ARMCPU { uint32_t id_isar3; uint32_t id_isar4; uint32_t id_isar5; + uint32_t clidr; + /* The elements of this array are the CCSIDR values for each cache, + * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. + */ + uint32_t ccsidr[16]; } ARMCPU; static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 924aaed..63de462 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -269,6 +269,10 @@ static void cortex_a8_initfn(Object *obj) cpu->id_isar2 = 0x21232031; cpu->id_isar3 = 0x11112131; cpu->id_isar4 = 0x00111142; + cpu->clidr = (1 << 27) | (2 << 24) | 3; + cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ + cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ + cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ } static void cortex_a9_initfn(Object *obj) @@ -302,6 +306,9 @@ static void cortex_a9_initfn(Object *obj) cpu->id_isar2 = 0x21232041; cpu->id_isar3 = 0x11112131; cpu->id_isar4 = 0x00111142; + cpu->clidr = (1 << 27) | (2 << 24) | 3; + cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */ + cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */ } static void cortex_a15_initfn(Object *obj) @@ -333,6 +340,10 @@ static void cortex_a15_initfn(Object *obj) cpu->id_isar2 = 0x21232041; cpu->id_isar3 = 0x11112131; cpu->id_isar4 = 0x10011142; + cpu->clidr = 0x0a200023; + cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ + cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ + cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ } static void ti925t_initfn(Object *obj) diff --git a/target-arm/helper.c b/target-arm/helper.c index fb618a7..5cbc7e0 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -25,21 +25,10 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_ARM11MPCORE: break; case ARM_CPUID_CORTEXA8: - env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3; - env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */ - env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */ - env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */ break; case ARM_CPUID_CORTEXA9: - env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3; - env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */ - env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */ break; case ARM_CPUID_CORTEXA15: - env->cp15.c0_clid = 0x0a200023; - env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */ - env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */ - env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */ break; case ARM_CPUID_CORTEXM3: break; @@ -113,6 +102,8 @@ void cpu_state_reset(CPUARMState *env) env->cp15.c0_c2[4] = cpu->id_isar4; env->cp15.c0_c2[5] = cpu->id_isar5; env->cp15.c15_i_min = 0xff0; + env->cp15.c0_clid = cpu->clidr; + memcpy(env->cp15.c0_ccsid, cpu->ccsidr, ARRAY_SIZE(cpu->ccsidr)); if (arm_feature(env, ARM_FEATURE_IWMMXT)) { env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';