From patchwork Sat Apr 14 16:42:23 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7820 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 1442423E4C for ; Sat, 14 Apr 2012 16:42:31 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id B0798A185C2 for ; Sat, 14 Apr 2012 16:42:30 +0000 (UTC) Received: by iage36 with SMTP id e36so7596938iag.11 for ; Sat, 14 Apr 2012 09:42:30 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=x/tMEh5A2vVQ1yc443JJzYeZsdxMP8W4jxxa7uaNsgQ=; b=FfIta7kexMGhtAf8SuoZ1CM/m699jqkcXeAERW3sYj9QlnV0p40ufgvl1pHsVKrxVi HiJifpp07WYn8RuV3RkZcEv7aSfDw6mlGlkBz7SwV9iCh5ZcHLnEzi9ZZXoQXIwX5EKa 3BgJPtfNEHX9EabDU4tErAE0c5BdMBXudVQ3oMVuSzNFqqiP4JfKvKyhOCYvaQ0iaQWF Elb/Q6WfOZZPx5U6PaR0sONLt3cqy7Gben28nHZmQxp+PImOuqJcghBZZMSfvskEBrIp uDaj0+QaGtHqSwIIQcFfH+kdyuN3rcIXQjdf4AZXyD5+XJHJqa4SzWtGllbQgRWj8Ozf FFkg== Received: by 10.42.152.134 with SMTP id i6mr3569763icw.27.1334421750169; Sat, 14 Apr 2012 09:42:30 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.70.69 with SMTP id c5csp90362ibj; Sat, 14 Apr 2012 09:42:29 -0700 (PDT) Received: by 10.180.88.199 with SMTP id bi7mr5204554wib.12.1334421748663; Sat, 14 Apr 2012 09:42:28 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id w71si13054421weq.126.2012.04.14.09.42.28 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 14 Apr 2012 09:42:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SJ63N-00087G-0e; Sat, 14 Apr 2012 17:42:25 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook , Anthony Liguori , Mark Langsdorf Subject: [PATCH v2 14/14] target-arm: Move A9 config_base_address reset value to ARMCPU Date: Sat, 14 Apr 2012 17:42:23 +0100 Message-Id: <1334421743-31146-16-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1334421743-31146-1-git-send-email-peter.maydell@linaro.org> References: <1334421743-31146-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQkYfdFPiViUzJSRESBJvLZ066Nfyfyo4q2R8RY4kaIwLJiAzGwY+k7hVdYzmS49Ho4QXFDS Move the A9 config_base_address cp15 register reset value to ARMCPU. This should become a QOM property so that the Highbank board can set it without having to pull in cpu-qom.h, but at least this avoids the implicit dependency on reset ordering that the previous workaround had. Cc: Mark Langsdorf Signed-off-by: Peter Maydell --- hw/highbank.c | 11 ++++------- target-arm/cpu-qom.h | 1 + target-arm/cpu.c | 4 +--- 3 files changed, 6 insertions(+), 10 deletions(-) diff --git a/hw/highbank.c b/hw/highbank.c index 906eed5..9ff639b 100644 --- a/hw/highbank.c +++ b/hw/highbank.c @@ -35,12 +35,6 @@ #define NIRQ_GIC 160 /* Board init. */ -static void highbank_cpu_reset(void *opaque) -{ - CPUARMState *env = opaque; - - env->cp15.c15_config_base_address = GIC_BASE_ADDR; -} static void hb_write_secondary(CPUARMState *env, const struct arm_boot_info *info) { @@ -213,14 +207,17 @@ static void highbank_init(ram_addr_t ram_size, } for (n = 0; n < smp_cpus; n++) { + ARMCPU *cpu; env = cpu_init(cpu_model); if (!env) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } + cpu = arm_env_get_cpu(env); + /* This will become a QOM property eventually */ + cpu->reset_cbar = GIC_BASE_ADDR; irqp = arm_pic_init_cpu(env); cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; - qemu_register_reset(highbank_cpu_reset, env); } sysmem = get_system_memory(); diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index b6c044a..4abfa90 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -94,6 +94,7 @@ typedef struct ARMCPU { * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. */ uint32_t ccsidr[16]; + uint32_t reset_cbar; } ARMCPU; static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 77347b0..8f5e309 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -30,7 +30,6 @@ static void arm_cpu_reset(CPUState *s) ARMCPU *cpu = ARM_CPU(s); ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); CPUARMState *env = &cpu->env; - uint32_t tmp = 0; if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); @@ -39,9 +38,8 @@ static void arm_cpu_reset(CPUState *s) acc->parent_reset(s); - tmp = env->cp15.c15_config_base_address; memset(env, 0, offsetof(CPUARMState, breakpoints)); - env->cp15.c15_config_base_address = tmp; + env->cp15.c15_config_base_address = cpu->reset_cbar; env->cp15.c0_cpuid = cpu->midr; env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;