From patchwork Sun Apr 15 13:46:03 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7865 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id EDC6B23E4C for ; Sun, 15 Apr 2012 13:56:52 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 8B9DDA181B4 for ; Sun, 15 Apr 2012 13:56:52 +0000 (UTC) Received: by iage36 with SMTP id e36so8552637iag.11 for ; Sun, 15 Apr 2012 06:56:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=el7QykdGhWWH1WhpqqJJbQhICh8tLZT2qMN2n+M58Lc=; b=VC2UCpZX0+2W7+TQqVXvhRBD4FEjjnZBuuEeO2hFiNOmkmIMPJwiLq9IwGMuaLjkOJ sXj2n5BzSJdLWisNQIRibuJwGXl0p93QKw9/wHm0prCVzkBGJTvcUbPgT2Lk6Tqn4Ysg ay3DlylMg/KdjEM3LVbOzo9gaJGL5penpBFWZC1j8IzlB6n2ef1cdPQ+zA7fa5t30mvv +vd8iTezIXw5Papp1C/QkgfCDn53G0ya+qe5uOPlwWVytzW16v9+3iLPVxBcJOKWFr1E Mqy16EXDsh/+3vzRovR8TxaG4+ANpzaGnhRCI9x3qS91UPWycZHe8JBmjXoc4idNw1si E2bw== Received: by 10.50.149.163 with SMTP id ub3mr3082188igb.30.1334498211894; Sun, 15 Apr 2012 06:56:51 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.70.69 with SMTP id c5csp22609ibj; Sun, 15 Apr 2012 06:56:51 -0700 (PDT) Received: by 10.180.104.137 with SMTP id ge9mr10768021wib.20.1334498210797; Sun, 15 Apr 2012 06:56:50 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id en6si4833169wid.45.2012.04.15.06.56.49 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 15 Apr 2012 06:56:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SJPmc-0000Ep-Ix; Sun, 15 Apr 2012 14:46:26 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Subject: [PATCH 10/32] target-arm: Convert TLS registers Date: Sun, 15 Apr 2012 14:46:03 +0100 Message-Id: <1334497585-867-11-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> References: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQnColzsFrjwEsqPJ3xp7BAfVn/E5QVxFahxN20x91pxtZ2nuJE8x9/UIe+F7OzbSSipjsiH Convert TLS registers to the new cp15 framework Signed-off-by: Peter Maydell --- target-arm/helper.c | 19 +++++++++++++++ target-arm/translate.c | 58 ------------------------------------------------ 2 files changed, 19 insertions(+), 58 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 391c126..eec111c 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -160,6 +160,22 @@ static const ARMCPRegInfo t2ee_cp_reginfo[] = { REGINFO_SENTINEL }; +static const ARMCPRegInfo v6k_cp_reginfo[] = { + { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, + .access = PL0_RW, + .fieldoffset = offsetof(CPUARMState, cp15.c13_tls1), + .resetvalue = 0 }, + { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, + .access = PL0_R|PL1_W, + .fieldoffset = offsetof(CPUARMState, cp15.c13_tls2), + .resetvalue = 0 }, + { .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.c13_tls3), + .resetvalue = 0 }, + REGINFO_SENTINEL +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -175,6 +191,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) } else { define_arm_cp_regs(env, not_v6_cp_reginfo); } + if (arm_feature(env, ARM_FEATURE_V6K)) { + define_arm_cp_regs(env, v6k_cp_reginfo); + } if (arm_feature(env, ARM_FEATURE_V7)) { define_arm_cp_regs(env, v7_cp_reginfo); } else { diff --git a/target-arm/translate.c b/target-arm/translate.c index b51c754..fc8dbf8 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2460,64 +2460,9 @@ static int cp15_user_ok(CPUARMState *env, uint32_t insn) } return 0; } - - if (cpn == 13 && cpm == 0) { - /* TLS register. */ - if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT))) - return 1; - } return 0; } -static int cp15_tls_load_store(CPUARMState *env, DisasContext *s, uint32_t insn, uint32_t rd) -{ - TCGv tmp; - int cpn = (insn >> 16) & 0xf; - int cpm = insn & 0xf; - int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38); - - if (!arm_feature(env, ARM_FEATURE_V6K)) - return 0; - - if (!(cpn == 13 && cpm == 0)) - return 0; - - if (insn & ARM_CP_RW_BIT) { - switch (op) { - case 2: - tmp = load_cpu_field(cp15.c13_tls1); - break; - case 3: - tmp = load_cpu_field(cp15.c13_tls2); - break; - case 4: - tmp = load_cpu_field(cp15.c13_tls3); - break; - default: - return 0; - } - store_reg(s, rd, tmp); - - } else { - tmp = load_reg(s, rd); - switch (op) { - case 2: - store_cpu_field(tmp, cp15.c13_tls1); - break; - case 3: - store_cpu_field(tmp, cp15.c13_tls2); - break; - case 4: - store_cpu_field(tmp, cp15.c13_tls3); - break; - default: - tcg_temp_free_i32(tmp); - return 0; - } - } - return 1; -} - /* Disassemble system coprocessor (cp15) instruction. Return nonzero if instruction is not defined. */ static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn) @@ -2548,9 +2493,6 @@ static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn) rd = (insn >> 12) & 0xf; - if (cp15_tls_load_store(env, s, insn, rd)) - return 0; - tmp2 = tcg_const_i32(insn); if (insn & ARM_CP_RW_BIT) { tmp = tcg_temp_new_i32();