From patchwork Sun Apr 15 13:46:19 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7844 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 0644223E47 for ; Sun, 15 Apr 2012 13:46:41 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id BFC5EA18189 for ; Sun, 15 Apr 2012 13:46:40 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so8543068iag.11 for ; Sun, 15 Apr 2012 06:46:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=Qo0W7tgj7qfJ0ZnGdEVN4bgmyd9CYiVpTX0y2nVPFxg=; b=nxJBubCOsEo9NCWwrzPSTH0qkk9nrFbaAUfNdU708iXvF7dH+0WHeBurfwMVzgE8eZ zxB2Y3BP6uyv0KvFQS7UIfFvUgwGVjBnEdLMzCbRnzaLXiKT1J3Lvo7jCnE/UMbZrAj+ ftmSPDZh+AGkd7tUcuqJrQIHp/1+FTjXQRiNWe3s64a0eanF1getKAYOEoACBwtT7w6w RnA+Z/rWy4Az8kPOkav2fzfi8BCILzTxmgGEHSSLheSSBjJOzktPWOJGG4Ic1GRw3jTc X941reZSumPelcAkw0q73HE7pxnsLIr5ABBnRwdMk0ndHZipIiEhFmJWrmvmChwvkL9e qWrg== Received: by 10.50.242.5 with SMTP id wm5mr3138383igc.40.1334497600551; Sun, 15 Apr 2012 06:46:40 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.70.69 with SMTP id c5csp22218ibj; Sun, 15 Apr 2012 06:46:39 -0700 (PDT) Received: by 10.216.139.204 with SMTP id c54mr4708437wej.103.1334497598574; Sun, 15 Apr 2012 06:46:38 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id k4si15345458weq.35.2012.04.15.06.46.37 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 15 Apr 2012 06:46:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SJPmd-0000FL-Nj; Sun, 15 Apr 2012 14:46:27 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Subject: [PATCH 26/32] target-arm: Convert cp15 cache ID registers Date: Sun, 15 Apr 2012 14:46:19 +0100 Message-Id: <1334497585-867-27-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> References: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQnsZYa/CkeNceHj7Bv8oYibvpNqswZS5bilFzL7/cP/fynp9hv/vVuNmzCbUvO9FdbsNnAJ Convert the cp15 cache ID registers to the new scheme. Signed-off-by: Peter Maydell --- target-arm/cpu.c | 2 - target-arm/cpu.h | 2 - target-arm/helper.c | 61 +++++++++++++++++++++++++++----------------------- 3 files changed, 33 insertions(+), 32 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index f5a392b..d7863fe 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -77,8 +77,6 @@ static void arm_cpu_reset(CPUState *s) env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; env->cp15.c0_cachetype = cpu->ctr; - env->cp15.c0_clid = cpu->clidr; - memcpy(env->cp15.c0_ccsid, cpu->ccsidr, ARRAY_SIZE(cpu->ccsidr)); if (arm_feature(env, ARM_FEATURE_IWMMXT)) { env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 26bce2e..850e0d6 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -108,8 +108,6 @@ typedef struct CPUARMState { struct { uint32_t c0_cpuid; uint32_t c0_cachetype; - uint32_t c0_ccsid[16]; /* Cache size. */ - uint32_t c0_clid; /* Cache level. */ uint32_t c0_cssel; /* Cache size selection. */ uint32_t c1_sys; /* System control register. */ uint32_t c1_coproc; /* Coprocessor access register. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index b16ab07..c13a483 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -197,6 +197,9 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = { { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), .resetvalue = 0 }, + /* v6 doesn't have the cache ID registers but Linux reads them anyway */ + { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, REGINFO_SENTINEL }; @@ -326,6 +329,21 @@ static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, return 0; } +static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t *value) +{ + ARMCPU *cpu = arm_env_get_cpu(env); + *value = cpu->ccsidr[env->cp15.c0_cssel]; + return 0; +} + +static int csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->cp15.c0_cssel = value & 0xf; + return 0; +} + static const ARMCPRegInfo v7_cp_reginfo[] = { /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped * debug components @@ -396,6 +414,16 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), .resetvalue = 0, }, + { .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, + .access = PL1_R, .readfn = ccsidr_read }, + { .name = "CSSELR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel), + .writefn = csselr_write, .resetvalue = 0 }, + /* Auxiliary ID register: this actually has an IMPDEF value but for now + * just RAZ for all cores: + */ + { .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7, + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, REGINFO_SENTINEL }; @@ -900,7 +928,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), .readfn = pmreg_read, .writefn = pmcr_write }; + ARMCPRegInfo clidr = { + .name = "CLIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr + }; define_one_arm_cp_reg(env, &pmcr); + define_one_arm_cp_reg(env, &clidr); define_arm_cp_regs(env, v7_cp_reginfo); } else { define_arm_cp_regs(env, not_v7_cp_reginfo); @@ -2037,11 +2070,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val) break; if (arm_feature(env, ARM_FEATURE_OMAPCP)) break; - if (arm_feature(env, ARM_FEATURE_V7) - && op1 == 2 && crm == 0 && op2 == 0) { - env->cp15.c0_cssel = val & 0xf; - break; - } goto bad_reg; case 4: /* Reserved. */ goto bad_reg; @@ -2109,29 +2137,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn) default: goto bad_reg; } - case 1: - /* These registers aren't documented on arm11 cores. However - Linux looks at them anyway. */ - if (!arm_feature(env, ARM_FEATURE_V6)) - goto bad_reg; - if (crm != 0) - goto bad_reg; - if (!arm_feature(env, ARM_FEATURE_V7)) - return 0; - - switch (op2) { - case 0: - return env->cp15.c0_ccsid[env->cp15.c0_cssel]; - case 1: - return env->cp15.c0_clid; - case 7: - return 0; - } - goto bad_reg; - case 2: - if (op2 != 0 || crm != 0) - goto bad_reg; - return env->cp15.c0_cssel; default: goto bad_reg; }