From patchwork Sun Apr 15 13:46:22 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7852 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id CB30D23E47 for ; Sun, 15 Apr 2012 13:46:49 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 90B76A181A5 for ; Sun, 15 Apr 2012 13:46:49 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so8543068iag.11 for ; Sun, 15 Apr 2012 06:46:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=RKGE1JN+uVH71Wq+DlbnrVyNLVN0o2ShcZni4HzfR+0=; b=VhDi1gRXUcJDgHiEp2kwg2rX42tpLHmFCYmNylG/v/0Cs9TbIxb1FMhofdc/MKZw+S UPP1HiweRVhil3S1AnUOiktLeEsyD7xfZr3VX1LDs67BgPzU+Vo9uhBSxGVbuzWjADmk s1123dKx8FxZEWxoP5IHrx2w1ILyT3RqA7RettZZpvDt2Bj20bS7E5FGy/LpXnPXl2VT n2h45fvWt0iJ5T6znyPtOMwDZWD08QgDR2IdFGai+I03O/Fzehg4IbRAQP0lcJaFOuCV rUf4nYY9HHcsLINd++C30jQf087YM2/fbD1VFO/tMoGs/8vdOyi4yBQD7WAoXT9cAQVS EppA== Received: by 10.50.187.137 with SMTP id fs9mr3125466igc.50.1334497609364; Sun, 15 Apr 2012 06:46:49 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.70.69 with SMTP id c5csp22245ibj; Sun, 15 Apr 2012 06:46:48 -0700 (PDT) Received: by 10.216.138.135 with SMTP id a7mr4860324wej.19.1334497608225; Sun, 15 Apr 2012 06:46:48 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id u4si2177605wif.22.2012.04.15.06.46.47 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 15 Apr 2012 06:46:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SJPmd-0000FR-TQ; Sun, 15 Apr 2012 14:46:27 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Subject: [PATCH 29/32] target-arm: Remove c0_cachetype CPUARMState field Date: Sun, 15 Apr 2012 14:46:22 +0100 Message-Id: <1334497585-867-30-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> References: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQlAgy7+E7fHRqVUDzxI1xZHHAeBu2BeBjxCa9bIK2wSo6iU26qGy/oyZTKzDEqGDOScIyqJ Remove the no-longer-used CPUARMState c0_cachetype field. Although this was a constant register we had it in our migration state. Drop this (with resulting version bump) because for ARM currently we prefer cleaner migration code and have not stabilised migration format yet. Signed-off-by: Peter Maydell --- target-arm/cpu.h | 3 +-- target-arm/machine.c | 2 -- 2 files changed, 1 insertions(+), 4 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index e7cd584..ded0118 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -107,7 +107,6 @@ typedef struct CPUARMState { /* System control coprocessor (cp15) */ struct { uint32_t c0_cpuid; - uint32_t c0_cachetype; uint32_t c0_cssel; /* Cache size selection. */ uint32_t c1_sys; /* System control register. */ uint32_t c1_coproc; /* Coprocessor access register. */ @@ -663,7 +662,7 @@ static inline int cp_access_ok(CPUARMState *env, #define cpu_signal_handler cpu_arm_signal_handler #define cpu_list arm_cpu_list -#define CPU_SAVE_VERSION 6 +#define CPU_SAVE_VERSION 7 /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel diff --git a/target-arm/machine.c b/target-arm/machine.c index f66b8df..a2a75fb 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -21,7 +21,6 @@ void cpu_save(QEMUFile *f, void *opaque) qemu_put_be32(f, env->fiq_regs[i]); } qemu_put_be32(f, env->cp15.c0_cpuid); - qemu_put_be32(f, env->cp15.c0_cachetype); qemu_put_be32(f, env->cp15.c0_cssel); qemu_put_be32(f, env->cp15.c1_sys); qemu_put_be32(f, env->cp15.c1_coproc); @@ -139,7 +138,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) env->fiq_regs[i] = qemu_get_be32(f); } env->cp15.c0_cpuid = qemu_get_be32(f); - env->cp15.c0_cachetype = qemu_get_be32(f); env->cp15.c0_cssel = qemu_get_be32(f); env->cp15.c1_sys = qemu_get_be32(f); env->cp15.c1_coproc = qemu_get_be32(f);