From patchwork Mon May 14 19:03:00 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8608 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 545C623E61 for ; Mon, 14 May 2012 19:03:45 +0000 (UTC) Received: from mail-pz0-f52.google.com (mail-pz0-f52.google.com [209.85.210.52]) by fiordland.canonical.com (Postfix) with ESMTP id 07776A1880F for ; Mon, 14 May 2012 19:03:44 +0000 (UTC) Received: by dano14 with SMTP id o14so7632657dan.11 for ; Mon, 14 May 2012 12:03:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=5aBzMWAggm0/eV0Tn/Z+8Q6jDPvVe8HEuitUF8u21nE=; b=i39EBzN0HOc4TWXk7mU/9uiuJ+duTBT8Oh5fy67QbY8Ek5UI/eVG7Ep3Ky9LR0YS/1 J62f78bAJDzUcV2rRbgYidKrJVbom9YBR8oM3nKRyFy4kCFiB1hjgxoqlfunxwxJUk9b Y1o39BiKXV8oopZu1q9RhtoxUyFXde0mfprUPkkPVy+Gm+gOiJP8xIRdT5S109PGhx0f fgn//4+FjEEDSIHO3U3VshgihA/Nr0sMkzsDg9rw009pNiyILhQfFv5UJz+4hfAPgoha 0NYABRRWAQYR4FuHHPs5tX3T1RE97naaSSorK95IdUtJphJlKujU9+bDBK6+OqYDbL14 JPjw== Received: by 10.50.154.169 with SMTP id vp9mr4907991igb.53.1337022223845; Mon, 14 May 2012 12:03:43 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.35.72 with SMTP id o8csp365938ibd; Mon, 14 May 2012 12:03:39 -0700 (PDT) Received: by 10.68.217.233 with SMTP id pb9mr25181694pbc.59.1337022218398; Mon, 14 May 2012 12:03:38 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id hq5si716668pbc.123.2012.05.14.12.03.36 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 14 May 2012 12:03:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SU0YO-0005mq-7X; Mon, 14 May 2012 20:03:32 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Rusty Russell Subject: [PATCH qom-next v2 01/33] target-arm: Fix 11MPCore cache type register value Date: Mon, 14 May 2012 20:03:00 +0100 Message-Id: <1337022212-22219-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> References: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQnSUDDfWIrIyZzb6BSQOCafMKoD55kA+5wbpJduZ/NjBx88fkb9JWuZ5p1DmYAcWS+dLLCi Make the 11MPCore report a valid value in its cache type register (the previous value appears to have been incorrectly copied from the 1136/1176). In particular, do not report that we have an aliasing VIPT cache, because this causes Linux to attempt to use the v6 block cache ops which the 11MPCore doesn't actually have. (This causes no problems currently because we over-broadly provide those ops on all cores, but prevents us correctly narrowing the block ops down to those cores which actually implement them.) Signed-off-by: Peter Maydell --- target-arm/cpu.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 7eb323a..934894b 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -307,7 +307,7 @@ static void arm11mpcore_initfn(Object *obj) cpu->reset_fpsid = 0x410120b4; cpu->mvfr0 = 0x11111111; cpu->mvfr1 = 0x00000000; - cpu->ctr = 0x1dd20d2; + cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ cpu->id_pfr0 = 0x111; cpu->id_pfr1 = 0x1; cpu->id_dfr0 = 0;