From patchwork Mon Jan 21 12:50:53 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 14172 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 8D83F23E08 for ; Mon, 21 Jan 2013 12:51:02 +0000 (UTC) Received: from mail-vb0-f45.google.com (mail-vb0-f45.google.com [209.85.212.45]) by fiordland.canonical.com (Postfix) with ESMTP id 15A6DA188F2 for ; Mon, 21 Jan 2013 12:51:01 +0000 (UTC) Received: by mail-vb0-f45.google.com with SMTP id p1so2375350vbi.4 for ; Mon, 21 Jan 2013 04:51:01 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state; bh=EFuEtHHhOjnRi/shawhjmncteVKBKWaIp+TUyQDPDEw=; b=doxXAYE/InIkbL2aXLpUu0DmXBYEyuxGb5xnTGSjs0RbdlADulmBNFr4b8ZmCBa5jp qb1nbgtXNLeM5KuoCjBjEz8rSuoH8pZWFiP8Ybl6wUDUUN2U+nteA72qy1itmaxocmZj JJ6os7YOugE3opz0koxWiO6trfqtj/uWK4U8M9uB1+WUpeUwEcZp2wFOgNvVvTmFgv89 z7S0O3ZG/lOQfDNxnYd1JRWxCoVawW2IRDzBY+xxiY7eTcG4Vj+ENNoFkX1za6xzHj4Y ceprmfm24BM7MSignZsDbbHVdSDf4YH8rtutwi5oOGGY9mB8iljZP13sZsCdNx5Fa3J9 1U7g== X-Received: by 10.52.176.6 with SMTP id ce6mr16874664vdc.57.1358772661546; Mon, 21 Jan 2013 04:51:01 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.58.145.101 with SMTP id st5csp199545veb; Mon, 21 Jan 2013 04:51:00 -0800 (PST) X-Received: by 10.194.174.234 with SMTP id bv10mr26274207wjc.47.1358772658852; Mon, 21 Jan 2013 04:50:58 -0800 (PST) Received: from mnementh.archaic.org.uk (1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id p13si3849341wie.80.2013.01.21.04.50.57 (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 21 Jan 2013 04:50:58 -0800 (PST) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Authentication-Results: mx.google.com; spf=neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1TxGq1-0001vz-1n; Mon, 21 Jan 2013 12:50:57 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Blue Swirl Subject: [PATCH 3/6] hw/omap_dma, hw/omap_spi: Explicitly mark fallthroughs Date: Mon, 21 Jan 2013 12:50:53 +0000 Message-Id: <1358772656-7406-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1358772656-7406-1-git-send-email-peter.maydell@linaro.org> References: <1358772656-7406-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQmAKAT9TpKIj4oj9qt1dCoNU6zcwpSr+87dCTPfOHDf5tfoPTrI/tD5QWnj5uim1w4wki6T Explicitly mark the fallthroughs as intentional in the code pattern where we gradually increment an index before falling into the code to read/write that array entry: case THINGY_3: idx++; case THINGY_2: idx++; case THINGY_1: idx++; case THINGY_0: return s->thingy[idx]; This makes static analysers happy. Signed-off-by: Peter Maydell --- hw/omap_dma.c | 12 ++++++++++++ hw/omap_spi.c | 24 ++++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/hw/omap_dma.c b/hw/omap_dma.c index aec5874..0c878b6 100644 --- a/hw/omap_dma.c +++ b/hw/omap_dma.c @@ -1709,19 +1709,25 @@ static uint64_t omap_dma4_read(void *opaque, hwaddr addr, case 0x14: /* DMA4_IRQSTATUS_L3 */ irqn ++; + /* fall through */ case 0x10: /* DMA4_IRQSTATUS_L2 */ irqn ++; + /* fall through */ case 0x0c: /* DMA4_IRQSTATUS_L1 */ irqn ++; + /* fall through */ case 0x08: /* DMA4_IRQSTATUS_L0 */ return s->irqstat[irqn]; case 0x24: /* DMA4_IRQENABLE_L3 */ irqn ++; + /* fall through */ case 0x20: /* DMA4_IRQENABLE_L2 */ irqn ++; + /* fall through */ case 0x1c: /* DMA4_IRQENABLE_L1 */ irqn ++; + /* fall through */ case 0x18: /* DMA4_IRQENABLE_L0 */ return s->irqen[irqn]; @@ -1856,10 +1862,13 @@ static void omap_dma4_write(void *opaque, hwaddr addr, switch (addr) { case 0x14: /* DMA4_IRQSTATUS_L3 */ irqn ++; + /* fall through */ case 0x10: /* DMA4_IRQSTATUS_L2 */ irqn ++; + /* fall through */ case 0x0c: /* DMA4_IRQSTATUS_L1 */ irqn ++; + /* fall through */ case 0x08: /* DMA4_IRQSTATUS_L0 */ s->irqstat[irqn] &= ~value; if (!s->irqstat[irqn]) @@ -1868,10 +1877,13 @@ static void omap_dma4_write(void *opaque, hwaddr addr, case 0x24: /* DMA4_IRQENABLE_L3 */ irqn ++; + /* fall through */ case 0x20: /* DMA4_IRQENABLE_L2 */ irqn ++; + /* fall through */ case 0x1c: /* DMA4_IRQENABLE_L1 */ irqn ++; + /* fall through */ case 0x18: /* DMA4_IRQENABLE_L0 */ s->irqen[irqn] = value; return; diff --git a/hw/omap_spi.c b/hw/omap_spi.c index 42d5149..8ff01ed 100644 --- a/hw/omap_spi.c +++ b/hw/omap_spi.c @@ -167,32 +167,47 @@ static uint64_t omap_mcspi_read(void *opaque, hwaddr addr, return s->control; case 0x68: ch ++; + /* fall through */ case 0x54: ch ++; + /* fall through */ case 0x40: ch ++; + /* fall through */ case 0x2c: /* MCSPI_CHCONF */ return s->ch[ch].config; case 0x6c: ch ++; + /* fall through */ case 0x58: ch ++; + /* fall through */ case 0x44: ch ++; + /* fall through */ case 0x30: /* MCSPI_CHSTAT */ return s->ch[ch].status; case 0x70: ch ++; + /* fall through */ case 0x5c: ch ++; + /* fall through */ case 0x48: ch ++; + /* fall through */ case 0x34: /* MCSPI_CHCTRL */ return s->ch[ch].control; case 0x74: ch ++; + /* fall through */ case 0x60: ch ++; + /* fall through */ case 0x4c: ch ++; + /* fall through */ case 0x38: /* MCSPI_TX */ return s->ch[ch].tx; case 0x78: ch ++; + /* fall through */ case 0x64: ch ++; + /* fall through */ case 0x50: ch ++; + /* fall through */ case 0x3c: /* MCSPI_RX */ s->ch[ch].status &= ~(1 << 0); /* RXS */ ret = s->ch[ch].rx; @@ -269,8 +284,11 @@ static void omap_mcspi_write(void *opaque, hwaddr addr, break; case 0x68: ch ++; + /* fall through */ case 0x54: ch ++; + /* fall through */ case 0x40: ch ++; + /* fall through */ case 0x2c: /* MCSPI_CHCONF */ if ((value ^ s->ch[ch].config) & (3 << 14)) /* DMAR | DMAW */ omap_mcspi_dmarequest_update(s->ch + ch); @@ -283,8 +301,11 @@ static void omap_mcspi_write(void *opaque, hwaddr addr, break; case 0x70: ch ++; + /* fall through */ case 0x5c: ch ++; + /* fall through */ case 0x48: ch ++; + /* fall through */ case 0x34: /* MCSPI_CHCTRL */ if (value & ~s->ch[ch].control & 1) { /* EN */ s->ch[ch].control |= 1; @@ -294,8 +315,11 @@ static void omap_mcspi_write(void *opaque, hwaddr addr, break; case 0x74: ch ++; + /* fall through */ case 0x60: ch ++; + /* fall through */ case 0x4c: ch ++; + /* fall through */ case 0x38: /* MCSPI_TX */ s->ch[ch].tx = value; s->ch[ch].status &= ~(1 << 1); /* TXS */