From patchwork Mon Feb 4 13:44:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 14535 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id D470F23FEE for ; Mon, 4 Feb 2013 13:44:50 +0000 (UTC) Received: from mail-vb0-f52.google.com (mail-vb0-f52.google.com [209.85.212.52]) by fiordland.canonical.com (Postfix) with ESMTP id 76579A18276 for ; Mon, 4 Feb 2013 13:44:50 +0000 (UTC) Received: by mail-vb0-f52.google.com with SMTP id fa15so3901019vbb.11 for ; Mon, 04 Feb 2013 05:44:50 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state; bh=pHUGwODwdbInpL2HUpR0Yj1MhtOo+yhHRyUVQ8yvHH0=; b=nK6ZDeCG04GiZgkV4n1G2CUtKs8cT571QAFSgPkleac04B5ws2++qlkoXYZ1ElAZ64 DDPPG38C+Fa2Eu0q71QTcreqUsLRYmfHJdDidkBebYu2b/80uDR3I9pMzOBlIDClIdqe f/a9RLeLhPUtsIJZLpNIUs6/wgkglmPIOZs8QMCyDGX97CgqXEK5cXCHF8axXS4kO2Pm CW4lbQDRodxAdow1Y8B0RrW8cB91D+SRgWuMLCXqXPG/EgLj4l6KRnAdJGpJW8vBW1zp cRtFEi0PTLCqwkz9MB904NmjR0Oi0zZvcaMfugaLu2kFthYlgFtYdQKq/EvG4/vNow/I EPBQ== X-Received: by 10.220.219.204 with SMTP id hv12mr21766361vcb.71.1359985489959; Mon, 04 Feb 2013 05:44:49 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.58.252.8 with SMTP id zo8csp87658vec; Mon, 4 Feb 2013 05:44:49 -0800 (PST) X-Received: by 10.180.77.68 with SMTP id q4mr10634534wiw.10.1359985487939; Mon, 04 Feb 2013 05:44:47 -0800 (PST) Received: from mnementh.archaic.org.uk (1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id t4si3641369wje.24.2013.02.04.05.44.47 (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 04 Feb 2013 05:44:47 -0800 (PST) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Authentication-Results: mx.google.com; spf=neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1U2MLd-0007eb-GA; Mon, 04 Feb 2013 13:44:37 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Anthony Liguori Subject: [PATCH 09/10] hw/arm_sysctl: Implement SYS_CFG_OSC function Date: Mon, 4 Feb 2013 13:44:35 +0000 Message-Id: <1359985476-29380-10-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1359985476-29380-1-git-send-email-peter.maydell@linaro.org> References: <1359985476-29380-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQky6XxSCd0NswhWOb1QyQvf6I6l+4xazu2OjtK2J5b8NwzzNo+8w+tNZoSXx+Xa64yCSb2s Implement the SYS_CFG_OSC function. Since the idea of programmable clock rates doesn't make much sense for QEMU, we simply allow the clock rate to be read back as written. The number and value of the daughterboard oscillators varies between daughterboards, so we provide an array property to allow their reset values to be configured. Signed-off-by: Peter Maydell --- hw/arm_sysctl.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/hw/arm_sysctl.c b/hw/arm_sysctl.c index 961bb57..ff66f9b 100644 --- a/hw/arm_sysctl.c +++ b/hw/arm_sysctl.c @@ -35,13 +35,17 @@ typedef struct { uint32_t sys_cfgctrl; uint32_t sys_cfgstat; uint32_t sys_clcd; + uint32_t mb_clock[6]; + uint32_t *db_clock; uint32_t db_num_vsensors; uint32_t *db_voltage; + uint32_t db_num_clocks; + uint32_t *db_clock_reset; } arm_sysctl_state; static const VMStateDescription vmstate_arm_sysctl = { .name = "realview_sysctl", - .version_id = 3, + .version_id = 4, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_UINT32(leds, arm_sysctl_state), @@ -56,6 +60,9 @@ static const VMStateDescription vmstate_arm_sysctl = { VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2), VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2), VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3), + VMSTATE_UINT32_ARRAY_V(mb_clock, arm_sysctl_state, 6, 4), + VMSTATE_VARRAY_UINT32(db_clock, arm_sysctl_state, db_num_clocks, + 4, vmstate_info_uint32, uint32_t), VMSTATE_END_OF_LIST() } }; @@ -79,6 +86,7 @@ static int board_id(arm_sysctl_state *s) static void arm_sysctl_reset(DeviceState *d) { arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, SYS_BUS_DEVICE(d)); + int i; s->leds = 0; s->lockval = 0; @@ -86,6 +94,17 @@ static void arm_sysctl_reset(DeviceState *d) s->cfgdata2 = 0; s->flags = 0; s->resetlevel = 0; + /* Motherboard oscillators (in Hz) */ + s->mb_clock[0] = 50000000; /* Static memory clock: 50MHz */ + s->mb_clock[1] = 23750000; /* motherboard CLCD clock: 23.75MHz */ + s->mb_clock[2] = 24000000; /* IO FPGA peripheral clock: 24MHz */ + s->mb_clock[3] = 24000000; /* IO FPGA reserved clock: 24MHz */ + s->mb_clock[4] = 24000000; /* System bus global clock: 24MHz */ + s->mb_clock[5] = 24000000; /* IO FPGA reserved clock: 24MHz */ + /* Daughterboard oscillators: reset from property values */ + for (i = 0; i < s->db_num_clocks; i++) { + s->db_clock[i] = s->db_clock_reset[i]; + } if (board_id(s) == BOARD_ID_VEXPRESS) { /* On VExpress this register will RAZ/WI */ s->sys_clcd = 0; @@ -251,6 +270,18 @@ static bool vexpress_cfgctrl_read(arm_sysctl_state *s, unsigned int dcc, return true; } break; + case SYS_CFG_OSC: + if (site == SYS_CFG_SITE_MB && device < sizeof(s->mb_clock)) { + /* motherboard clock */ + *val = s->mb_clock[device]; + return true; + } + if (site == SYS_CFG_SITE_DB1 && device < s->db_num_clocks) { + /* daughterboard clock */ + *val = s->db_clock[device]; + return true; + } + break; default: break; } @@ -287,6 +318,18 @@ static bool vexpress_cfgctrl_write(arm_sysctl_state *s, unsigned int dcc, } switch (function) { + case SYS_CFG_OSC: + if (site == SYS_CFG_SITE_MB && device < sizeof(s->mb_clock)) { + /* motherboard clock */ + s->mb_clock[device] = val; + return true; + } + if (site == SYS_CFG_SITE_DB1 && device < s->db_num_clocks) { + /* daughterboard clock */ + s->db_clock[device] = val; + return true; + } + break; case SYS_CFG_MUXFPGA: if (site == SYS_CFG_SITE_MB && device == 0) { /* Select whether video output comes from motherboard @@ -551,11 +594,19 @@ static void arm_sysctl_init(Object *obj) qdev_init_gpio_out(&s->busdev.qdev, &s->pl110_mux_ctrl, 1); } +static void arm_sysctl_realize(DeviceState *d, Error **errp) +{ + arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, SYS_BUS_DEVICE(d)); + s->db_clock = g_new0(uint32_t, s->db_num_clocks); +} + static void arm_sysctl_finalize(Object *obj) { SysBusDevice *dev = SYS_BUS_DEVICE(obj); arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev); g_free(s->db_voltage); + g_free(s->db_clock); + g_free(s->db_clock_reset); } static Property arm_sysctl_properties[] = { @@ -564,6 +615,9 @@ static Property arm_sysctl_properties[] = { /* Daughterboard power supply voltages (as reported via SYS_CFG) */ DEFINE_PROP_ARRAY("db-voltage", arm_sysctl_state, db_num_vsensors, db_voltage, qdev_prop_uint32, uint32_t), + /* Daughterboard clock reset values (as reported via SYS_CFG) */ + DEFINE_PROP_ARRAY("db-clock", arm_sysctl_state, db_num_clocks, + db_clock_reset, qdev_prop_uint32, uint32_t), DEFINE_PROP_END_OF_LIST(), }; @@ -571,6 +625,7 @@ static void arm_sysctl_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + dc->realize = arm_sysctl_realize; dc->reset = arm_sysctl_reset; dc->vmsd = &vmstate_arm_sysctl; dc->props = arm_sysctl_properties;