From patchwork Tue Mar 26 10:22:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 15655 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id A94DE23E64 for ; Tue, 26 Mar 2013 10:22:21 +0000 (UTC) Received: from mail-ve0-f173.google.com (mail-ve0-f173.google.com [209.85.128.173]) by fiordland.canonical.com (Postfix) with ESMTP id 694DAA198C4 for ; Tue, 26 Mar 2013 10:22:21 +0000 (UTC) Received: by mail-ve0-f173.google.com with SMTP id cy12so894607veb.4 for ; Tue, 26 Mar 2013 03:22:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state; bh=ZQj42wa8hElBW1Ti1uUn3szKluJz31r9ClfM6nVoVuI=; b=OiR3qcRGLOyb6TSAuavfFuNCsFAeacwQYOuI7l4dv9vXrwZNPEEMDBkgPyAZkTuKGL vmFv54JoG7l3t4QrrzTsCX4NH0NoV5OeYChYqQJu7waO17W1OshA5H/mv16lGF/uZ+6E u5zidDa+k4NQeLmUjsfs+qql7SqGiRKphRgsawqFLZKdBBFsL6zbTSG07eTZj5vlDags g2Do7+ngDFzip8EoXuBPmJoDgNZUbw+uE+aIrJG92cRhK4WV5S8Tn7WLY+DXW3Mw2bJ9 BHW4QPBUQxYIi0UXkz4qEpcb8+msTx8Uq5qGvcFRkJ3ojsEr5jPsO/2Qf+eYMymzqFaD HNlQ== X-Received: by 10.220.106.14 with SMTP id v14mr2614581vco.2.1364293340964; Tue, 26 Mar 2013 03:22:20 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.59.4.204 with SMTP id cg12csp64347ved; Tue, 26 Mar 2013 03:22:20 -0700 (PDT) X-Received: by 10.204.201.1 with SMTP id ey1mr2558104bkb.110.1364293337184; Tue, 26 Mar 2013 03:22:17 -0700 (PDT) Received: from mnementh.archaic.org.uk (1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id ge5si5227984bkc.86.2013.03.26.03.22.16 (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 26 Mar 2013 03:22:17 -0700 (PDT) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Authentication-Results: mx.google.com; spf=neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1UKR1A-0002HP-Fn; Tue, 26 Mar 2013 10:22:12 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Arnd Bergmann , "Michael S. Tsirkin" , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Will Deacon , Paul Brook , Aurelien Jarno Subject: [PATCH v2 09/11] arm/realview: Fix mapping of PCI regions Date: Tue, 26 Mar 2013 10:22:09 +0000 Message-Id: <1364293331-8722-10-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1364293331-8722-1-git-send-email-peter.maydell@linaro.org> References: <1364293331-8722-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQkDxR9DAo+73mLbllEFpvH/BRgcUrHne7W+SnqAMyLJhgTEo/4qAFz/Cvb8g7DnpWYTEaF1 Fix the mapping of the PCI regions for the realview board, which were all incorrect. (This was never noticed because the Linux kernel doesn't actually include a PCI driver for the realview boards.) Signed-off-by: Peter Maydell --- hw/arm/realview.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/arm/realview.c b/hw/arm/realview.c index ba61d18..23c968b 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -218,9 +218,9 @@ static void realview_init(QEMUMachineInitArgs *args, busdev = SYS_BUS_DEVICE(dev); qdev_init_nofail(dev); sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */ - sysbus_mmio_map(busdev, 1, 0x61000000); /* PCI self-config */ - sysbus_mmio_map(busdev, 2, 0x62000000); /* PCI config */ - sysbus_mmio_map(busdev, 3, 0x63000000); /* PCI I/O */ + sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */ + sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */ + sysbus_mmio_map(busdev, 3, 0x62000000); /* PCI I/O */ sysbus_connect_irq(busdev, 0, pic[48]); sysbus_connect_irq(busdev, 1, pic[49]); sysbus_connect_irq(busdev, 2, pic[50]); @@ -304,12 +304,12 @@ static void realview_init(QEMUMachineInitArgs *args, /* 0x58000000 PISMO. */ /* 0x5c000000 PISMO. */ /* 0x60000000 PCI. */ - /* 0x61000000 PCI Self Config. */ - /* 0x62000000 PCI Config. */ - /* 0x63000000 PCI IO. */ - /* 0x64000000 PCI mem 0. */ - /* 0x68000000 PCI mem 1. */ - /* 0x6c000000 PCI mem 2. */ + /* 0x60000000 PCI Self Config. */ + /* 0x61000000 PCI Config. */ + /* 0x62000000 PCI IO. */ + /* 0x63000000 PCI mem 0. */ + /* 0x64000000 PCI mem 1. */ + /* 0x68000000 PCI mem 2. */ /* ??? Hack to map an additional page of ram for the secondary CPU startup code. I guess this works on real hardware because the