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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id z8si18395856eee.269.2013.06.13.05.51.41 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 13 Jun 2013 05:51:41 -0700 (PDT) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Un707-0002hd-VI; Thu, 13 Jun 2013 13:51:40 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH] target-arm: Make LPAE feature imply V7MP Date: Thu, 13 Jun 2013 13:51:39 +0100 Message-Id: <1371127899-10364-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 X-Gm-Message-State: ALoCoQkX+P4aPYCWw31+Rm+wEXnbUGyuxUkqyamT5w2Pkiu9ja3CHZfemkkpYAPEChxnHUt9e8XX X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.182 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The v7 ARM ARM specifies that the Large Physical Address Extension requires implementation of the Multiprocessing Extensions, so make our LPAE feature imply V7MP rather than specifying both in the A15 CPU initfn. Signed-off-by: Peter Maydell Reviewed-by: Andreas Färber --- Doesn't make much difference now, but will save a line when adding future CPU definitions. target-arm/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 496a59f..54b4bb2 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -198,6 +198,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) set_feature(env, ARM_FEATURE_VFP); } if (arm_feature(env, ARM_FEATURE_LPAE)) { + set_feature(env, ARM_FEATURE_V7MP); set_feature(env, ARM_FEATURE_PXN); } @@ -571,7 +572,6 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); - set_feature(&cpu->env, ARM_FEATURE_V7MP); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_LPAE);