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[67.169.181.221]) by mx.google.com with ESMTPSA id rz6sm19165159pab.22.2013.11.18.22.17.05 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 18 Nov 2013 22:17:06 -0800 (PST) From: Christoffer Dall To: qemu-devel@nongnu.org Cc: kvmarm@lists.cs.columbia.edu, patches@linaro.org, Christoffer Dall Subject: [RFC PATCH v3 02/10] hw: arm_gic: Introduce gic_set_priority function Date: Mon, 18 Nov 2013 22:18:08 -0800 Message-Id: <1384841896-19566-3-git-send-email-christoffer.dall@linaro.org> X-Mailer: git-send-email 1.8.4.3 In-Reply-To: <1384841896-19566-1-git-send-email-christoffer.dall@linaro.org> References: <1384841896-19566-1-git-send-email-christoffer.dall@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: christoffer.dall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.49 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , To make the code slightly cleaner to look at and make the save/restore code easier to understand, introduce this function to set the priority of interrupts. Reviewed-by: Peter Maydell Signed-off-by: Christoffer Dall --- hw/intc/arm_gic.c | 15 ++++++++++----- hw/intc/gic_internal.h | 1 + 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index c7a24d5..7eaa55f 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -169,6 +169,15 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu) return new_irq; } +void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val) +{ + if (irq < GIC_INTERNAL) { + s->priority1[irq][cpu] = val; + } else { + s->priority2[(irq) - GIC_INTERNAL] = val; + } +} + void gic_complete_irq(GICState *s, int cpu, int irq) { int update = 0; @@ -444,11 +453,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, irq = (offset - 0x400) + GIC_BASE_IRQ; if (irq >= s->num_irq) goto bad_reg; - if (irq < GIC_INTERNAL) { - s->priority1[irq][cpu] = value; - } else { - s->priority2[irq - GIC_INTERNAL] = value; - } + gic_set_priority(s, cpu, irq, value); } else if (offset < 0xc00) { /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the * annoying exception of the 11MPCore's GIC. diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 3989fd1..f916725 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -61,5 +61,6 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu); void gic_complete_irq(GICState *s, int cpu, int irq); void gic_update(GICState *s); void gic_init_irqs_and_distributor(GICState *s, int num_irq); +void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val); #endif /* !QEMU_ARM_GIC_INTERNAL_H */